📄 stm8s_clk.ls
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1915 ; 718 CLK->CSSR |= CLK_CSSR_CSSEN;
1917 0250 721050c8 bset 20680,#0
1918 ; 719 }
1921 0254 81 ret
1946 ; 736 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
1946 ; 737 {
1947 switch .text
1948 0255 _CLK_GetSYSCLKSource:
1952 ; 738 return((CLK_Source_TypeDef)CLK->CMSR);
1954 0255 c650c3 ld a,20675
1957 0258 81 ret
2014 ; 756 u32 CLK_GetClockFreq(void)
2014 ; 757 {
2015 switch .text
2016 0259 _CLK_GetClockFreq:
2018 0259 5209 subw sp,#9
2019 00000009 OFST: set 9
2022 ; 759 u32 clockfrequency = 0;
2024 ; 760 CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
2026 ; 761 u8 tmp = 0, presc = 0;
2030 ; 764 clocksource = (CLK_Source_TypeDef)CLK->CMSR;
2032 025b c650c3 ld a,20675
2033 025e 6b09 ld (OFST+0,sp),a
2034 ; 766 if (clocksource == CLK_SOURCE_HSI)
2036 0260 7b09 ld a,(OFST+0,sp)
2037 0262 a1e1 cp a,#225
2038 0264 2641 jrne L3701
2039 ; 768 tmp = (u8)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
2041 0266 c650c6 ld a,20678
2042 0269 a418 and a,#24
2043 026b 6b09 ld (OFST+0,sp),a
2044 ; 769 tmp = (u8)(tmp >> 3);
2046 026d 0409 srl (OFST+0,sp)
2047 026f 0409 srl (OFST+0,sp)
2048 0271 0409 srl (OFST+0,sp)
2049 ; 770 presc = HSIDivFactor[tmp];
2051 0273 7b09 ld a,(OFST+0,sp)
2052 0275 5f clrw x
2053 0276 97 ld xl,a
2054 0277 d60000 ld a,(_HSIDivFactor,x)
2055 027a 6b09 ld (OFST+0,sp),a
2056 ; 771 clockfrequency = HSI_VALUE / presc;
2058 027c 7b09 ld a,(OFST+0,sp)
2059 027e b703 ld c_lreg+3,a
2060 0280 3f02 clr c_lreg+2
2061 0282 3f01 clr c_lreg+1
2062 0284 3f00 clr c_lreg
2063 0286 96 ldw x,sp
2064 0287 1c0001 addw x,#OFST-8
2065 028a cd0000 call c_rtol
2067 028d ae2400 ldw x,#9216
2068 0290 bf02 ldw c_lreg+2,x
2069 0292 ae00f4 ldw x,#244
2070 0295 bf00 ldw c_lreg,x
2071 0297 96 ldw x,sp
2072 0298 1c0001 addw x,#OFST-8
2073 029b cd0000 call c_ludv
2075 029e 96 ldw x,sp
2076 029f 1c0005 addw x,#OFST-4
2077 02a2 cd0000 call c_rtol
2080 02a5 201c jra L5701
2081 02a7 L3701:
2082 ; 773 else if ( clocksource == CLK_SOURCE_LSI)
2084 02a7 7b09 ld a,(OFST+0,sp)
2085 02a9 a1d2 cp a,#210
2086 02ab 260c jrne L7701
2087 ; 775 clockfrequency = LSI_VALUE;
2089 02ad aef400 ldw x,#62464
2090 02b0 1f07 ldw (OFST-2,sp),x
2091 02b2 ae0001 ldw x,#1
2092 02b5 1f05 ldw (OFST-4,sp),x
2094 02b7 200a jra L5701
2095 02b9 L7701:
2096 ; 779 clockfrequency = HSE_VALUE;
2098 02b9 ae3600 ldw x,#13824
2099 02bc 1f07 ldw (OFST-2,sp),x
2100 02be ae016e ldw x,#366
2101 02c1 1f05 ldw (OFST-4,sp),x
2102 02c3 L5701:
2103 ; 782 return((u32)clockfrequency);
2105 02c3 96 ldw x,sp
2106 02c4 1c0005 addw x,#OFST-4
2107 02c7 cd0000 call c_ltor
2111 02ca 5b09 addw sp,#9
2112 02cc 81 ret
2211 ; 800 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
2211 ; 801 {
2212 switch .text
2213 02cd _CLK_AdjustHSICalibrationValue:
2215 02cd 88 push a
2216 00000000 OFST: set 0
2219 ; 804 assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
2221 ; 807 CLK->HSITRIMR = (u8)((CLK->HSITRIMR & (u8)(~CLK_HSITRIMR_HSITRIM))|((u8)CLK_HSICalibrationValue));
2223 02ce c650cc ld a,20684
2224 02d1 a4f8 and a,#248
2225 02d3 1a01 or a,(OFST+1,sp)
2226 02d5 c750cc ld 20684,a
2227 ; 809 }
2230 02d8 84 pop a
2231 02d9 81 ret
2255 ; 828 void CLK_SYSCLKEmergencyClear(void)
2255 ; 829 {
2256 switch .text
2257 02da _CLK_SYSCLKEmergencyClear:
2261 ; 830 CLK->SWCR &= (u8)(~CLK_SWCR_SWBSY);
2263 02da 721150c5 bres 20677,#0
2264 ; 831 }
2267 02de 81 ret
2416 ; 847 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
2416 ; 848 {
2417 switch .text
2418 02df _CLK_GetFlagStatus:
2420 02df 89 pushw x
2421 02e0 5203 subw sp,#3
2422 00000003 OFST: set 3
2425 ; 850 u16 statusreg = 0;
2427 ; 851 u8 tmpreg = 0;
2429 ; 852 FlagStatus bitstatus = RESET;
2431 ; 855 assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
2433 ; 858 statusreg = (u16)((u16)CLK_FLAG & (u16)0xFF00);
2435 02e2 01 rrwa x,a
2436 02e3 9f ld a,xl
2437 02e4 a4ff and a,#255
2438 02e6 97 ld xl,a
2439 02e7 4f clr a
2440 02e8 02 rlwa x,a
2441 02e9 1f01 ldw (OFST-2,sp),x
2442 02eb 01 rrwa x,a
2443 ; 861 if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
2445 02ec 1e01 ldw x,(OFST-2,sp)
2446 02ee a30100 cpw x,#256
2447 02f1 2607 jrne L1421
2448 ; 863 tmpreg = CLK->ICKR;
2450 02f3 c650c0 ld a,20672
2451 02f6 6b03 ld (OFST+0,sp),a
2453 02f8 202f jra L3421
2454 02fa L1421:
2455 ; 865 else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
2457 02fa 1e01 ldw x,(OFST-2,sp)
2458 02fc a30200 cpw x,#512
2459 02ff 2607 jrne L5421
2460 ; 867 tmpreg = CLK->ECKR;
2462 0301 c650c1 ld a,20673
2463 0304 6b03 ld (OFST+0,sp),a
2465 0306 2021 jra L3421
2466 0308 L5421:
2467 ; 869 else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
2469 0308 1e01 ldw x,(OFST-2,sp)
2470 030a a30300 cpw x,#768
2471 030d 2607 jrne L1521
2472 ; 871 tmpreg = CLK->SWCR;
2474 030f c650c5 ld a,20677
2475 0312 6b03 ld (OFST+0,sp),a
2477 0314 2013 jra L3421
2478 0316 L1521:
2479 ; 873 else if (statusreg == 0x0400) /* The flag to check is in CSS register */
2481 0316 1e01 ldw x,(OFST-2,sp)
2482 0318 a30400 cpw x,#1024
2483 031b 2607 jrne L5521
2484 ; 875 tmpreg = CLK->CSSR;
2486 031d c650c8 ld a,20680
2487 0320 6b03 ld (OFST+0,sp),a
2489 0322 2005 jra L3421
2490 0324 L5521:
2491 ; 879 tmpreg = CLK->CCOR;
2493 0324 c650c9 ld a,20681
2494 0327 6b03 ld (OFST+0,sp),a
2495 0329 L3421:
2496 ; 882 if ((tmpreg & (u8)CLK_FLAG) != (u8)RESET)
2498 0329 7b05 ld a,(OFST+2,sp)
2499 032b 1503 bcp a,(OFST+0,sp)
2500 032d 2706 jreq L1621
2501 ; 884 bitstatus = SET;
2503 032f a601 ld a,#1
2504 0331 6b03 ld (OFST+0,sp),a
2506 0333 2002 jra L3621
2507 0335 L1621:
2508 ; 888 bitstatus = RESET;
2510 0335 0f03 clr (OFST+0,sp)
2511 0337 L3621:
2512 ; 892 return((FlagStatus)bitstatus);
2514 0337 7b03 ld a,(OFST+0,sp)
2517 0339 5b05 addw sp,#5
2518 033b 81 ret
2564 ; 913 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
2564 ; 914 {
2565 switch .text
2566 033c _CLK_GetITStatus:
2568 033c 88 push a
2569 033d 88 push a
2570 00000001 OFST: set 1
2573 ; 916 ITStatus bitstatus = RESET;
2575 ; 919 assert_param(IS_CLK_IT_OK(CLK_IT));
2577 ; 921 if (CLK_IT == CLK_IT_SWIF)
2579 033e a11c cp a,#28
2580 0340 2611 jrne L7031
2581 ; 924 if ((CLK->SWCR & (u8)CLK_IT) == (u8)0x0C)
2583 0342 c450c5 and a,20677
2584 0345 a10c cp a,#12
2585 0347 2606 jrne L1131
2586 ; 926 bitstatus = SET;
2588 0349 a601 ld a,#1
2589 034b 6b01 ld (OFST+0,sp),a
2591 034d 2015 jra L5131
2592 034f L1131:
2593 ; 930 bitstatus = RESET;
2595 034f 0f01 clr (OFST+0,sp)
2596 0351 2011 jra L5131
2597 0353 L7031:
2598 ; 936 if ((CLK->CSSR & (u8)CLK_IT) == (u8)0x0C)
2600 0353 c650c8 ld a,20680
2601 0356 1402 and a,(OFST+1,sp)
2602 0358 a10c cp a,#12
2603 035a 2606 jrne L7131
2604 ; 938 bitstatus = SET;
2606 035c a601 ld a,#1
2607 035e 6b01 ld (OFST+0,sp),a
2609 0360 2002 jra L5131
2610 0362 L7131:
2611 ; 942 bitstatus = RESET;
2613 0362 0f01 clr (OFST+0,sp)
2614 0364 L5131:
2615 ; 947 return bitstatus;
2617 0364 7b01 ld a,(OFST+0,sp)
2620 0366 85 popw x
2621 0367 81 ret
2657 ; 966 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
2657 ; 967 {
2658 switch .text
2659 0368 _CLK_ClearITPendingBit:
2663 ; 970 assert_param(IS_CLK_IT_OK(CLK_IT));
2665 ; 972 if (CLK_IT == (u8)CLK_IT_CSSD)
2667 0368 a10c cp a,#12
2668 036a 2606 jrne L1431
2669 ; 975 CLK->CSSR &= (u8)(~CLK_CSSR_CSSD);
2671 036c 721750c8 bres 20680,#3
2673 0370 2004 jra L3431
2674 0372 L1431:
2675 ; 980 CLK->SWCR &= (u8)(~CLK_SWCR_SWIF);
2677 0372 721750c5 bres 20677,#3
2678 0376 L3431:
2679 ; 983 }
2682 0376 81 ret
2717 xdef _CLKPrescTable
2718 xdef _HSIDivFactor
2719 xdef _CLK_ClearITPendingBit
2720 xdef _CLK_GetITStatus
2721 xdef _CLK_GetFlagStatus
2722 xdef _CLK_GetSYSCLKSource
2723 xdef _CLK_GetClockFreq
2724 xdef _CLK_AdjustHSICalibrationValue
2725 xdef _CLK_SYSCLKEmergencyClear
2726 xdef _CLK_ClockSecuritySystemEnable
2727 xdef _CLK_CANConfig
2728 xdef _CLK_SWIMConfig
2729 xdef _CLK_SYSCLKConfig
2730 xdef _CLK_ITConfig
2731 xdef _CLK_CCOConfig
2732 xdef _CLK_HSIPrescalerConfig
2733 xdef _CLK_ClockSwitchConfig
2734 xdef _CLK_PeripheralClockConfig
2735 xdef _CLK_SlowActiveHaltWakeUpCmd
2736 xdef _CLK_FastHaltWakeUpCmd
2737 xdef _CLK_ClockSwitchCmd
2738 xdef _CLK_CCOCmd
2739 xdef _CLK_LSICmd
2740 xdef _CLK_HSICmd
2741 xdef _CLK_HSECmd
2742 xdef _CLK_DeInit
2743 xref.b c_lreg
2744 xref.b c_x
2763 xref c_ltor
2764 xref c_ludv
2765 xref c_rtol
2766 end
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