📄 stm8s_clk.ls
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1000 ; 415 assert_param(IS_FUNCTIONALSTATE_OK(CLK_SwitchIT));
1002 ; 416 assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
1004 ; 419 clock_master = (CLK_Source_TypeDef)CLK->CMSR;
1006 0112 c650c3 ld a,20675
1007 0115 6b01 ld (OFST-3,sp),a
1008 ; 422 if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)
1010 0117 7b05 ld a,(OFST+1,sp)
1011 0119 a101 cp a,#1
1012 011b 2639 jrne L534
1013 ; 426 CLK->SWCR |= CLK_SWCR_SWEN;
1015 011d 721250c5 bset 20677,#1
1016 ; 429 if (CLK_SwitchIT != DISABLE)
1018 0121 0d09 tnz (OFST+5,sp)
1019 0123 2706 jreq L734
1020 ; 431 CLK->SWCR |= CLK_SWCR_SWIEN;
1022 0125 721450c5 bset 20677,#2
1024 0129 2004 jra L144
1025 012b L734:
1026 ; 435 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1028 012b 721550c5 bres 20677,#2
1029 012f L144:
1030 ; 439 CLK->SWR = (u8)CLK_NewClock;
1032 012f 7b06 ld a,(OFST+2,sp)
1033 0131 c750c4 ld 20676,a
1035 0134 2007 jra L744
1036 0136 L344:
1037 ; 443 DownCounter--;
1039 0136 1e03 ldw x,(OFST-1,sp)
1040 0138 1d0001 subw x,#1
1041 013b 1f03 ldw (OFST-1,sp),x
1042 013d L744:
1043 ; 441 while (((CLK->SWCR & CLK_SWCR_SWBSY) && (DownCounter != 0)))
1045 013d c650c5 ld a,20677
1046 0140 a501 bcp a,#1
1047 0142 2704 jreq L354
1049 0144 1e03 ldw x,(OFST-1,sp)
1050 0146 26ee jrne L344
1051 0148 L354:
1052 ; 446 if (DownCounter != 0)
1054 0148 1e03 ldw x,(OFST-1,sp)
1055 014a 2706 jreq L554
1056 ; 448 Swif = SUCCESS;
1058 014c a601 ld a,#1
1059 014e 6b02 ld (OFST-2,sp),a
1061 0150 201b jra L164
1062 0152 L554:
1063 ; 452 Swif = ERROR;
1065 0152 0f02 clr (OFST-2,sp)
1066 0154 2017 jra L164
1067 0156 L534:
1068 ; 460 if (CLK_SwitchIT != DISABLE)
1070 0156 0d09 tnz (OFST+5,sp)
1071 0158 2706 jreq L364
1072 ; 462 CLK->SWCR |= CLK_SWCR_SWIEN;
1074 015a 721450c5 bset 20677,#2
1076 015e 2004 jra L564
1077 0160 L364:
1078 ; 466 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1080 0160 721550c5 bres 20677,#2
1081 0164 L564:
1082 ; 470 CLK->SWR = (u8)CLK_NewClock;
1084 0164 7b06 ld a,(OFST+2,sp)
1085 0166 c750c4 ld 20676,a
1086 ; 474 Swif = SUCCESS;
1088 0169 a601 ld a,#1
1089 016b 6b02 ld (OFST-2,sp),a
1090 016d L164:
1091 ; 479 if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
1093 016d 0d0a tnz (OFST+6,sp)
1094 016f 260c jrne L764
1096 0171 7b01 ld a,(OFST-3,sp)
1097 0173 a1e1 cp a,#225
1098 0175 2606 jrne L764
1099 ; 481 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
1101 0177 721150c0 bres 20672,#0
1103 017b 201e jra L174
1104 017d L764:
1105 ; 483 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
1107 017d 0d0a tnz (OFST+6,sp)
1108 017f 260c jrne L374
1110 0181 7b01 ld a,(OFST-3,sp)
1111 0183 a1d2 cp a,#210
1112 0185 2606 jrne L374
1113 ; 485 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
1115 0187 721750c0 bres 20672,#3
1117 018b 200e jra L174
1118 018d L374:
1119 ; 487 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
1121 018d 0d0a tnz (OFST+6,sp)
1122 018f 260a jrne L174
1124 0191 7b01 ld a,(OFST-3,sp)
1125 0193 a1b4 cp a,#180
1126 0195 2604 jrne L174
1127 ; 489 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
1129 0197 721150c1 bres 20673,#0
1130 019b L174:
1131 ; 492 return(Swif);
1133 019b 7b02 ld a,(OFST-2,sp)
1136 019d 5b06 addw sp,#6
1137 019f 81 ret
1275 ; 509 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
1275 ; 510 {
1276 switch .text
1277 01a0 _CLK_HSIPrescalerConfig:
1279 01a0 88 push a
1280 00000000 OFST: set 0
1283 ; 513 assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
1285 ; 516 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1287 01a1 c650c6 ld a,20678
1288 01a4 a4e7 and a,#231
1289 01a6 c750c6 ld 20678,a
1290 ; 519 CLK->CKDIVR |= (u8)HSIPrescaler;
1292 01a9 c650c6 ld a,20678
1293 01ac 1a01 or a,(OFST+1,sp)
1294 01ae c750c6 ld 20678,a
1295 ; 521 }
1298 01b1 84 pop a
1299 01b2 81 ret
1434 ; 539 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
1434 ; 540 {
1435 switch .text
1436 01b3 _CLK_CCOConfig:
1438 01b3 88 push a
1439 00000000 OFST: set 0
1442 ; 543 assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
1444 ; 546 CLK->CCOR &= (u8)(~CLK_CCOR_CCOSEL);
1446 01b4 c650c9 ld a,20681
1447 01b7 a4e1 and a,#225
1448 01b9 c750c9 ld 20681,a
1449 ; 549 CLK->CCOR |= (u8)CLK_CCO;
1451 01bc c650c9 ld a,20681
1452 01bf 1a01 or a,(OFST+1,sp)
1453 01c1 c750c9 ld 20681,a
1454 ; 552 CLK->CCOR |= CLK_CCOR_CCOEN;
1456 01c4 721050c9 bset 20681,#0
1457 ; 554 }
1460 01c8 84 pop a
1461 01c9 81 ret
1526 ; 571 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState IT_NewState)
1526 ; 572 {
1527 switch .text
1528 01ca _CLK_ITConfig:
1530 01ca 89 pushw x
1531 00000000 OFST: set 0
1534 ; 575 assert_param(IS_FUNCTIONALSTATE_OK(IT_NewState));
1536 ; 576 assert_param(IS_CLK_IT_OK(CLK_IT));
1538 ; 578 if (IT_NewState != DISABLE)
1540 01cb 9f ld a,xl
1541 01cc 4d tnz a
1542 01cd 2719 jreq L576
1543 ; 580 switch (CLK_IT)
1545 01cf 9e ld a,xh
1547 ; 588 default:
1547 ; 589 break;
1548 01d0 a00c sub a,#12
1549 01d2 270a jreq L136
1550 01d4 a010 sub a,#16
1551 01d6 2624 jrne L307
1552 ; 582 case CLK_IT_SWIF: /* Enable the clock switch interrupt */
1552 ; 583 CLK->SWCR |= CLK_SWCR_SWIEN;
1554 01d8 721450c5 bset 20677,#2
1555 ; 584 break;
1557 01dc 201e jra L307
1558 01de L136:
1559 ; 585 case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
1559 ; 586 CLK->CSSR |= CLK_CSSR_CSSDIE;
1561 01de 721450c8 bset 20680,#2
1562 ; 587 break;
1564 01e2 2018 jra L307
1565 01e4 L336:
1566 ; 588 default:
1566 ; 589 break;
1568 01e4 2016 jra L307
1569 01e6 L107:
1571 01e6 2014 jra L307
1572 01e8 L576:
1573 ; 594 switch (CLK_IT)
1575 01e8 7b01 ld a,(OFST+1,sp)
1577 ; 602 default:
1577 ; 603 break;
1578 01ea a00c sub a,#12
1579 01ec 270a jreq L736
1580 01ee a010 sub a,#16
1581 01f0 260a jrne L307
1582 ; 596 case CLK_IT_SWIF: /* Disable the clock switch interrupt */
1582 ; 597 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1584 01f2 721550c5 bres 20677,#2
1585 ; 598 break;
1587 01f6 2004 jra L307
1588 01f8 L736:
1589 ; 599 case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
1589 ; 600 CLK->CSSR &= (u8)(~CLK_CSSR_CSSDIE);
1591 01f8 721550c8 bres 20680,#2
1592 ; 601 break;
1593 01fc L307:
1594 ; 607 }
1597 01fc 85 popw x
1598 01fd 81 ret
1599 01fe L146:
1600 ; 602 default:
1600 ; 603 break;
1602 01fe 20fc jra L307
1603 0200 L707:
1604 0200 20fa jra L307
1639 ; 623 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef ClockPrescaler)
1639 ; 624 {
1640 switch .text
1641 0202 _CLK_SYSCLKConfig:
1643 0202 88 push a
1644 00000000 OFST: set 0
1647 ; 627 assert_param(IS_CLK_PRESCALER_OK(ClockPrescaler));
1649 ; 629 if (((u8)ClockPrescaler & (u8)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
1651 0203 a580 bcp a,#128
1652 0205 2614 jrne L727
1653 ; 631 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1655 0207 c650c6 ld a,20678
1656 020a a4e7 and a,#231
1657 020c c750c6 ld 20678,a
1658 ; 632 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_HSIDIV);
1660 020f 7b01 ld a,(OFST+1,sp)
1661 0211 a418 and a,#24
1662 0213 ca50c6 or a,20678
1663 0216 c750c6 ld 20678,a
1665 0219 2012 jra L137
1666 021b L727:
1667 ; 636 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_CPUDIV);
1669 021b c650c6 ld a,20678
1670 021e a4f8 and a,#248
1671 0220 c750c6 ld 20678,a
1672 ; 637 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_CPUDIV);
1674 0223 7b01 ld a,(OFST+1,sp)
1675 0225 a407 and a,#7
1676 0227 ca50c6 or a,20678
1677 022a c750c6 ld 20678,a
1678 022d L137:
1679 ; 640 }
1682 022d 84 pop a
1683 022e 81 ret
1739 ; 654 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
1739 ; 655 {
1740 switch .text
1741 022f _CLK_SWIMConfig:
1745 ; 658 assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
1747 ; 660 if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
1749 022f 4d tnz a
1750 0230 2706 jreq L167
1751 ; 663 CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
1753 0232 721050cd bset 20685,#0
1755 0236 2004 jra L367
1756 0238 L167:
1757 ; 668 CLK->SWIMCCR &= (u8)(~CLK_SWIMCCR_SWIMDIV);
1759 0238 721150cd bres 20685,#0
1760 023c L367:
1761 ; 671 }
1764 023c 81 ret
1861 ; 686 void CLK_CANConfig(CLK_CANDivider_TypeDef CLK_CANDivider)
1861 ; 687 {
1862 switch .text
1863 023d _CLK_CANConfig:
1865 023d 88 push a
1866 00000000 OFST: set 0
1869 ; 690 assert_param(IS_CLK_CANDIVIDER_OK(CLK_CANDivider));
1871 ; 693 CLK->CANCCR &= (u8)(~CLK_CANCCR_CANDIV);
1873 023e c650cb ld a,20683
1874 0241 a4f8 and a,#248
1875 0243 c750cb ld 20683,a
1876 ; 696 CLK->CANCCR |= (u8)CLK_CANDivider;
1878 0246 c650cb ld a,20683
1879 0249 1a01 or a,(OFST+1,sp)
1880 024b c750cb ld 20683,a
1881 ; 698 }
1884 024e 84 pop a
1885 024f 81 ret
1909 ; 715 void CLK_ClockSecuritySystemEnable(void)
1909 ; 716 {
1910 switch .text
1911 0250 _CLK_ClockSecuritySystemEnable:
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