📄 stm8s_clk.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.8.32.1 - 30 Mar 2010
3 ; Generator V4.3.4 - 23 Mar 2010
15 .const: section .text
16 0000 _HSIDivFactor:
17 0000 01 dc.b 1
18 0001 02 dc.b 2
19 0002 04 dc.b 4
20 0003 08 dc.b 8
21 0004 _CLKPrescTable:
22 0004 01 dc.b 1
23 0005 02 dc.b 2
24 0006 04 dc.b 4
25 0007 08 dc.b 8
26 0008 0a dc.b 10
27 0009 10 dc.b 16
28 000a 14 dc.b 20
29 000b 28 dc.b 40
58 ; 83 void CLK_DeInit(void)
58 ; 84 {
60 switch .text
61 0000 _CLK_DeInit:
65 ; 86 CLK->ICKR = CLK_ICKR_RESET_VALUE;
67 0000 350150c0 mov 20672,#1
68 ; 87 CLK->ECKR = CLK_ECKR_RESET_VALUE;
70 0004 725f50c1 clr 20673
71 ; 88 CLK->SWR = CLK_SWR_RESET_VALUE;
73 0008 35e150c4 mov 20676,#225
74 ; 89 CLK->SWCR = CLK_SWCR_RESET_VALUE;
76 000c 725f50c5 clr 20677
77 ; 90 CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
79 0010 351850c6 mov 20678,#24
80 ; 91 CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
82 0014 35ff50c7 mov 20679,#255
83 ; 92 CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
85 0018 35ff50ca mov 20682,#255
86 ; 93 CLK->CSSR = CLK_CSSR_RESET_VALUE;
88 001c 725f50c8 clr 20680
89 ; 95 CLK->CCOR = CLK_CCOR_RESET_VALUE;
91 0020 725f50c9 clr 20681
93 0024 L52:
94 ; 96 while (CLK->CCOR & CLK_CCOR_CCOEN)
96 0024 c650c9 ld a,20681
97 0027 a501 bcp a,#1
98 0029 26f9 jrne L52
99 ; 98 CLK->CCOR = CLK_CCOR_RESET_VALUE;
101 002b 725f50c9 clr 20681
102 ; 100 CLK->CANCCR = CLK_CANCCR_RESET_VALUE;
104 002f 725f50cb clr 20683
105 ; 101 CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
107 0033 725f50cc clr 20684
108 ; 102 CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
110 0037 725f50cd clr 20685
111 ; 104 }
114 003b 81 ret
170 ; 123 void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
170 ; 124 {
171 switch .text
172 003c _CLK_FastHaltWakeUpCmd:
176 ; 127 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
178 ; 129 if (NewState != DISABLE)
180 003c 4d tnz a
181 003d 2706 jreq L75
182 ; 132 CLK->ICKR |= CLK_ICKR_FHWU;
184 003f 721450c0 bset 20672,#2
186 0043 2004 jra L16
187 0045 L75:
188 ; 137 CLK->ICKR &= (u8)(~CLK_ICKR_FHWU);
190 0045 721550c0 bres 20672,#2
191 0049 L16:
192 ; 140 }
195 0049 81 ret
230 ; 154 void CLK_HSECmd(FunctionalState CLK_NewState)
230 ; 155 {
231 switch .text
232 004a _CLK_HSECmd:
236 ; 158 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
238 ; 160 if (CLK_NewState != DISABLE)
240 004a 4d tnz a
241 004b 2706 jreq L101
242 ; 163 CLK->ECKR |= CLK_ECKR_HSEEN;
244 004d 721050c1 bset 20673,#0
246 0051 2004 jra L301
247 0053 L101:
248 ; 168 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
250 0053 721150c1 bres 20673,#0
251 0057 L301:
252 ; 171 }
255 0057 81 ret
290 ; 185 void CLK_HSICmd(FunctionalState CLK_NewState)
290 ; 186 {
291 switch .text
292 0058 _CLK_HSICmd:
296 ; 189 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
298 ; 191 if (CLK_NewState != DISABLE)
300 0058 4d tnz a
301 0059 2706 jreq L321
302 ; 194 CLK->ICKR |= CLK_ICKR_HSIEN;
304 005b 721050c0 bset 20672,#0
306 005f 2004 jra L521
307 0061 L321:
308 ; 199 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
310 0061 721150c0 bres 20672,#0
311 0065 L521:
312 ; 202 }
315 0065 81 ret
350 ; 216 void CLK_LSICmd(FunctionalState CLK_NewState)
350 ; 217 {
351 switch .text
352 0066 _CLK_LSICmd:
356 ; 220 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
358 ; 222 if (CLK_NewState != DISABLE)
360 0066 4d tnz a
361 0067 2706 jreq L541
362 ; 225 CLK->ICKR |= CLK_ICKR_LSIEN;
364 0069 721650c0 bset 20672,#3
366 006d 2004 jra L741
367 006f L541:
368 ; 230 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
370 006f 721750c0 bres 20672,#3
371 0073 L741:
372 ; 233 }
375 0073 81 ret
410 ; 248 void CLK_CCOCmd(FunctionalState CLK_NewState)
410 ; 249 {
411 switch .text
412 0074 _CLK_CCOCmd:
416 ; 252 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
418 ; 254 if (CLK_NewState != DISABLE)
420 0074 4d tnz a
421 0075 2706 jreq L761
422 ; 257 CLK->CCOR |= CLK_CCOR_CCOEN;
424 0077 721050c9 bset 20681,#0
426 007b 2004 jra L171
427 007d L761:
428 ; 262 CLK->CCOR &= (u8)(~CLK_CCOR_CCOEN);
430 007d 721150c9 bres 20681,#0
431 0081 L171:
432 ; 265 }
435 0081 81 ret
470 ; 281 void CLK_ClockSwitchCmd(FunctionalState CLK_NewState)
470 ; 282 {
471 switch .text
472 0082 _CLK_ClockSwitchCmd:
476 ; 285 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
478 ; 287 if (CLK_NewState != DISABLE )
480 0082 4d tnz a
481 0083 2706 jreq L112
482 ; 290 CLK->SWCR |= CLK_SWCR_SWEN;
484 0085 721250c5 bset 20677,#1
486 0089 2004 jra L312
487 008b L112:
488 ; 295 CLK->SWCR &= (u8)(~CLK_SWCR_SWEN);
490 008b 721350c5 bres 20677,#1
491 008f L312:
492 ; 298 }
495 008f 81 ret
531 ; 315 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
531 ; 316 {
532 switch .text
533 0090 _CLK_SlowActiveHaltWakeUpCmd:
537 ; 319 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
539 ; 321 if (NewState != DISABLE)
541 0090 4d tnz a
542 0091 2706 jreq L332
543 ; 324 CLK->ICKR |= CLK_ICKR_SWUAH;
545 0093 721a50c0 bset 20672,#5
547 0097 2004 jra L532
548 0099 L332:
549 ; 329 CLK->ICKR &= (u8)(~CLK_ICKR_SWUAH);
551 0099 721b50c0 bres 20672,#5
552 009d L532:
553 ; 332 }
556 009d 81 ret
691 ; 349 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState CLK_NewState)
691 ; 350 {
692 switch .text
693 009e _CLK_PeripheralClockConfig:
695 009e 89 pushw x
696 00000000 OFST: set 0
699 ; 353 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
701 ; 354 assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
703 ; 356 if (((u8)CLK_Peripheral & (u8)0x10) == 0x00)
705 009f 9e ld a,xh
706 00a0 a510 bcp a,#16
707 00a2 2633 jrne L313
708 ; 358 if (CLK_NewState != DISABLE)
710 00a4 0d02 tnz (OFST+2,sp)
711 00a6 2717 jreq L513
712 ; 361 CLK->PCKENR1 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
714 00a8 7b01 ld a,(OFST+1,sp)
715 00aa a40f and a,#15
716 00ac 5f clrw x
717 00ad 97 ld xl,a
718 00ae a601 ld a,#1
719 00b0 5d tnzw x
720 00b1 2704 jreq L62
721 00b3 L03:
722 00b3 48 sll a
723 00b4 5a decw x
724 00b5 26fc jrne L03
725 00b7 L62:
726 00b7 ca50c7 or a,20679
727 00ba c750c7 ld 20679,a
729 00bd 2049 jra L123
730 00bf L513:
731 ; 366 CLK->PCKENR1 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
733 00bf 7b01 ld a,(OFST+1,sp)
734 00c1 a40f and a,#15
735 00c3 5f clrw x
736 00c4 97 ld xl,a
737 00c5 a601 ld a,#1
738 00c7 5d tnzw x
739 00c8 2704 jreq L23
740 00ca L43:
741 00ca 48 sll a
742 00cb 5a decw x
743 00cc 26fc jrne L43
744 00ce L23:
745 00ce 43 cpl a
746 00cf c450c7 and a,20679
747 00d2 c750c7 ld 20679,a
748 00d5 2031 jra L123
749 00d7 L313:
750 ; 371 if (CLK_NewState != DISABLE)
752 00d7 0d02 tnz (OFST+2,sp)
753 00d9 2717 jreq L323
754 ; 374 CLK->PCKENR2 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
756 00db 7b01 ld a,(OFST+1,sp)
757 00dd a40f and a,#15
758 00df 5f clrw x
759 00e0 97 ld xl,a
760 00e1 a601 ld a,#1
761 00e3 5d tnzw x
762 00e4 2704 jreq L63
763 00e6 L04:
764 00e6 48 sll a
765 00e7 5a decw x
766 00e8 26fc jrne L04
767 00ea L63:
768 00ea ca50ca or a,20682
769 00ed c750ca ld 20682,a
771 00f0 2016 jra L123
772 00f2 L323:
773 ; 379 CLK->PCKENR2 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
775 00f2 7b01 ld a,(OFST+1,sp)
776 00f4 a40f and a,#15
777 00f6 5f clrw x
778 00f7 97 ld xl,a
779 00f8 a601 ld a,#1
780 00fa 5d tnzw x
781 00fb 2704 jreq L24
782 00fd L44:
783 00fd 48 sll a
784 00fe 5a decw x
785 00ff 26fc jrne L44
786 0101 L24:
787 0101 43 cpl a
788 0102 c450ca and a,20682
789 0105 c750ca ld 20682,a
790 0108 L123:
791 ; 383 }
794 0108 85 popw x
795 0109 81 ret
981 ; 405 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState CLK_SwitchIT, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
981 ; 406 {
982 switch .text
983 010a _CLK_ClockSwitchConfig:
985 010a 89 pushw x
986 010b 5204 subw sp,#4
987 00000004 OFST: set 4
990 ; 409 u16 DownCounter = CLK_TIMEOUT;
992 010d ae0491 ldw x,#1169
993 0110 1f03 ldw (OFST-1,sp),x
994 ; 410 ErrorStatus Swif = ERROR;
996 ; 413 assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
998 ; 414 assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
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