📄 stm8s_itc.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.8.32.1 - 30 Mar 2010
3 ; Generator V4.3.4 - 23 Mar 2010
43 ; 62 u8 ITC_GetCPUCC(void)
43 ; 63 {
45 switch .text
46 0000 _ITC_GetCPUCC:
50 ; 64 _asm("push cc");
53 0000 8a push cc
55 ; 65 _asm("pop a");
58 0001 84 pop a
60 ; 66 return; /* Ignore compiler warning, the returned value is in A register */
63 0002 81 ret
86 ; 97 void ITC_DeInit(void)
86 ; 98 {
87 switch .text
88 0003 _ITC_DeInit:
92 ; 99 ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
94 0003 35ff7f70 mov 32624,#255
95 ; 100 ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
97 0007 35ff7f71 mov 32625,#255
98 ; 101 ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
100 000b 35ff7f72 mov 32626,#255
101 ; 102 ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
103 000f 35ff7f73 mov 32627,#255
104 ; 103 ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
106 0013 35ff7f74 mov 32628,#255
107 ; 104 ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
109 0017 35ff7f75 mov 32629,#255
110 ; 105 ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
112 001b 35ff7f76 mov 32630,#255
113 ; 106 ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
115 001f 35ff7f77 mov 32631,#255
116 ; 107 }
119 0023 81 ret
144 ; 124 u8 ITC_GetSoftIntStatus(void)
144 ; 125 {
145 switch .text
146 0024 _ITC_GetSoftIntStatus:
150 ; 126 return (u8)(ITC_GetCPUCC() & CPU_CC_I1I0);
152 0024 adda call _ITC_GetCPUCC
154 0026 a428 and a,#40
157 0028 81 ret
430 .const: section .text
431 0000 L22:
432 0000 004c dc.w L14
433 0002 004c dc.w L14
434 0004 004c dc.w L14
435 0006 004c dc.w L14
436 0008 0055 dc.w L34
437 000a 0055 dc.w L34
438 000c 0055 dc.w L34
439 000e 0055 dc.w L34
440 0010 005e dc.w L54
441 0012 005e dc.w L54
442 0014 005e dc.w L54
443 0016 005e dc.w L54
444 0018 0067 dc.w L74
445 001a 0067 dc.w L74
446 001c 0067 dc.w L74
447 001e 0067 dc.w L74
448 0020 0070 dc.w L15
449 0022 0070 dc.w L15
450 0024 0070 dc.w L15
451 0026 0070 dc.w L15
452 0028 0079 dc.w L35
453 002a 0079 dc.w L35
454 002c 0079 dc.w L35
455 002e 0079 dc.w L35
456 0030 0082 dc.w L55
457 ; 144 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
457 ; 145 {
458 switch .text
459 0029 _ITC_GetSoftwarePriority:
461 0029 88 push a
462 002a 89 pushw x
463 00000002 OFST: set 2
466 ; 147 u8 Value = 0;
468 002b 0f02 clr (OFST+0,sp)
469 ; 151 assert_param(IS_ITC_IRQ_OK((u8)IrqNum));
471 ; 154 Mask = (u8)(0x03U << (((u8)IrqNum % 4U) * 2U));
473 002d a403 and a,#3
474 002f 48 sll a
475 0030 5f clrw x
476 0031 97 ld xl,a
477 0032 a603 ld a,#3
478 0034 5d tnzw x
479 0035 2704 jreq L41
480 0037 L61:
481 0037 48 sll a
482 0038 5a decw x
483 0039 26fc jrne L61
484 003b L41:
485 003b 6b01 ld (OFST-1,sp),a
486 ; 156 switch (IrqNum)
488 003d 7b03 ld a,(OFST+1,sp)
490 ; 197 default:
490 ; 198 break;
491 003f a119 cp a,#25
492 0041 2407 jruge L02
493 0043 5f clrw x
494 0044 97 ld xl,a
495 0045 58 sllw x
496 0046 de0000 ldw x,(L22,x)
497 0049 fc jp (x)
498 004a L02:
499 004a 203d jra L702
500 004c L14:
501 ; 158 case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */
501 ; 159 case ITC_IRQ_AWU:
501 ; 160 case ITC_IRQ_CLK:
501 ; 161 case ITC_IRQ_PORTA:
501 ; 162 Value = (u8)(ITC->ISPR1 & Mask); /* Read software priority */
503 004c c67f70 ld a,32624
504 004f 1401 and a,(OFST-1,sp)
505 0051 6b02 ld (OFST+0,sp),a
506 ; 163 break;
508 0053 2034 jra L702
509 0055 L34:
510 ; 164 case ITC_IRQ_PORTB:
510 ; 165 case ITC_IRQ_PORTC:
510 ; 166 case ITC_IRQ_PORTD:
510 ; 167 case ITC_IRQ_PORTE:
510 ; 168 Value = (u8)(ITC->ISPR2 & Mask); /* Read software priority */
512 0055 c67f71 ld a,32625
513 0058 1401 and a,(OFST-1,sp)
514 005a 6b02 ld (OFST+0,sp),a
515 ; 169 break;
517 005c 202b jra L702
518 005e L54:
519 ; 170 case ITC_IRQ_CAN_RX:
519 ; 171 case ITC_IRQ_CAN_TX:
519 ; 172 case ITC_IRQ_SPI:
519 ; 173 case ITC_IRQ_TIM1_OVF:
519 ; 174 Value = (u8)(ITC->ISPR3 & Mask); /* Read software priority */
521 005e c67f72 ld a,32626
522 0061 1401 and a,(OFST-1,sp)
523 0063 6b02 ld (OFST+0,sp),a
524 ; 175 break;
526 0065 2022 jra L702
527 0067 L74:
528 ; 176 case ITC_IRQ_TIM1_CAPCOM:
528 ; 177 case ITC_IRQ_TIM2_OVF:
528 ; 178 case ITC_IRQ_TIM2_CAPCOM:
528 ; 179 case ITC_IRQ_TIM3_OVF:
528 ; 180 Value = (u8)(ITC->ISPR4 & Mask); /* Read software priority */
530 0067 c67f73 ld a,32627
531 006a 1401 and a,(OFST-1,sp)
532 006c 6b02 ld (OFST+0,sp),a
533 ; 181 break;
535 006e 2019 jra L702
536 0070 L15:
537 ; 182 case ITC_IRQ_TIM3_CAPCOM:
537 ; 183 case ITC_IRQ_USART_TX:
537 ; 184 case ITC_IRQ_USART_RX:
537 ; 185 case ITC_IRQ_I2C:
537 ; 186 Value = (u8)(ITC->ISPR5 & Mask); /* Read software priority */
539 0070 c67f74 ld a,32628
540 0073 1401 and a,(OFST-1,sp)
541 0075 6b02 ld (OFST+0,sp),a
542 ; 187 break;
544 0077 2010 jra L702
545 0079 L35:
546 ; 188 case ITC_IRQ_LINUART_TX:
546 ; 189 case ITC_IRQ_LINUART_RX:
546 ; 190 case ITC_IRQ_ADC:
546 ; 191 case ITC_IRQ_TIM4_OVF:
546 ; 192 Value = (u8)(ITC->ISPR6 & Mask); /* Read software priority */
548 0079 c67f75 ld a,32629
549 007c 1401 and a,(OFST-1,sp)
550 007e 6b02 ld (OFST+0,sp),a
551 ; 193 break;
553 0080 2007 jra L702
554 0082 L55:
555 ; 194 case ITC_IRQ_EEPROM_EEC:
555 ; 195 Value = (u8)(ITC->ISPR7 & Mask); /* Read software priority */
557 0082 c67f76 ld a,32630
558 0085 1401 and a,(OFST-1,sp)
559 0087 6b02 ld (OFST+0,sp),a
560 ; 196 break;
562 0089 L75:
563 ; 197 default:
563 ; 198 break;
565 0089 L702:
566 ; 201 Value >>= (u8)(((u8)IrqNum % 4u) * 2u);
568 0089 7b03 ld a,(OFST+1,sp)
569 008b a403 and a,#3
570 008d 48 sll a
571 008e 5f clrw x
572 008f 97 ld xl,a
573 0090 7b02 ld a,(OFST+0,sp)
574 0092 5d tnzw x
575 0093 2704 jreq L42
576 0095 L62:
577 0095 44 srl a
578 0096 5a decw x
579 0097 26fc jrne L62
580 0099 L42:
581 0099 6b02 ld (OFST+0,sp),a
582 ; 203 return((ITC_PriorityLevel_TypeDef)Value);
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