📄 stm8s_adc1.ls
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2121 02d1 5d tnzw x
2122 02d2 2704 jreq L211
2123 02d4 L411:
2124 02d4 48 sll a
2125 02d5 5a decw x
2126 02d6 26fc jrne L411
2127 02d8 L211:
2128 02d8 c4540c and a,21516
2129 02db 6b01 ld (OFST+0,sp),a
2130 02dd L7001:
2131 ; 706 return ((FlagStatus)status);
2133 02dd 7b01 ld a,(OFST+0,sp)
2136 02df 85 popw x
2137 02e0 81 ret
2284 ; 725 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag)
2284 ; 726 {
2285 switch .text
2286 02e1 _ADC1_GetFlagStatus:
2288 02e1 88 push a
2289 02e2 88 push a
2290 00000001 OFST: set 1
2293 ; 727 u8 flagstatus = 0;
2295 ; 728 u8 temp = 0;
2297 ; 731 assert_param(IS_ADC1_FLAG_OK(Flag));
2299 ; 733 if ((Flag & 0x0F) == 0x01)
2301 02e3 a40f and a,#15
2302 02e5 a101 cp a,#1
2303 02e7 2609 jrne L1701
2304 ; 736 flagstatus = (u8)(ADC1->CR3 & ADC1_CR3_OVR);
2306 02e9 c65403 ld a,21507
2307 02ec a440 and a,#64
2308 02ee 6b01 ld (OFST+0,sp),a
2310 02f0 2045 jra L3701
2311 02f2 L1701:
2312 ; 738 else if ((Flag & 0xF0) == 0x10)
2314 02f2 7b02 ld a,(OFST+1,sp)
2315 02f4 a4f0 and a,#240
2316 02f6 a110 cp a,#16
2317 02f8 2636 jrne L5701
2318 ; 741 temp = (u8)(Flag & 0x0F);
2320 02fa 7b02 ld a,(OFST+1,sp)
2321 02fc a40f and a,#15
2322 02fe 6b01 ld (OFST+0,sp),a
2323 ; 742 if (temp < 8)
2325 0300 7b01 ld a,(OFST+0,sp)
2326 0302 a108 cp a,#8
2327 0304 2414 jruge L7701
2328 ; 744 flagstatus = (u8)(ADC1->AWSRL & (1 << temp));
2330 0306 7b01 ld a,(OFST+0,sp)
2331 0308 5f clrw x
2332 0309 97 ld xl,a
2333 030a a601 ld a,#1
2334 030c 5d tnzw x
2335 030d 2704 jreq L021
2336 030f L221:
2337 030f 48 sll a
2338 0310 5a decw x
2339 0311 26fc jrne L221
2340 0313 L021:
2341 0313 c4540d and a,21517
2342 0316 6b01 ld (OFST+0,sp),a
2344 0318 201d jra L3701
2345 031a L7701:
2346 ; 748 flagstatus = (u8)(ADC1->AWSRH & (1 << (temp - 8)));
2348 031a 7b01 ld a,(OFST+0,sp)
2349 031c a008 sub a,#8
2350 031e 5f clrw x
2351 031f 97 ld xl,a
2352 0320 a601 ld a,#1
2353 0322 5d tnzw x
2354 0323 2704 jreq L421
2355 0325 L621:
2356 0325 48 sll a
2357 0326 5a decw x
2358 0327 26fc jrne L621
2359 0329 L421:
2360 0329 c4540c and a,21516
2361 032c 6b01 ld (OFST+0,sp),a
2362 032e 2007 jra L3701
2363 0330 L5701:
2364 ; 753 flagstatus = (u8)(ADC1->CSR & Flag);
2366 0330 c65400 ld a,21504
2367 0333 1402 and a,(OFST+1,sp)
2368 0335 6b01 ld (OFST+0,sp),a
2369 0337 L3701:
2370 ; 755 return ((FlagStatus)flagstatus);
2372 0337 7b01 ld a,(OFST+0,sp)
2375 0339 85 popw x
2376 033a 81 ret
2418 ; 774 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag)
2418 ; 775 {
2419 switch .text
2420 033b _ADC1_ClearFlag:
2422 033b 88 push a
2423 033c 88 push a
2424 00000001 OFST: set 1
2427 ; 776 u8 temp = 0;
2429 ; 779 assert_param(IS_ADC1_FLAG_OK(Flag));
2431 ; 781 if ((Flag & 0x0F) == 0x01)
2433 033d a40f and a,#15
2434 033f a101 cp a,#1
2435 0341 2606 jrne L5211
2436 ; 784 ADC1->CR3 &= (u8)(~ADC1_CR3_OVR);
2438 0343 721d5403 bres 21507,#6
2440 0347 204b jra L7211
2441 0349 L5211:
2442 ; 786 else if ((Flag & 0xF0) == 0x10)
2444 0349 7b02 ld a,(OFST+1,sp)
2445 034b a4f0 and a,#240
2446 034d a110 cp a,#16
2447 034f 263a jrne L1311
2448 ; 789 temp = (u8)(Flag & 0x0F);
2450 0351 7b02 ld a,(OFST+1,sp)
2451 0353 a40f and a,#15
2452 0355 6b01 ld (OFST+0,sp),a
2453 ; 790 if (temp < 8)
2455 0357 7b01 ld a,(OFST+0,sp)
2456 0359 a108 cp a,#8
2457 035b 2416 jruge L3311
2458 ; 792 ADC1->AWSRL &= (u8)(~((u8)1 << temp));
2460 035d 7b01 ld a,(OFST+0,sp)
2461 035f 5f clrw x
2462 0360 97 ld xl,a
2463 0361 a601 ld a,#1
2464 0363 5d tnzw x
2465 0364 2704 jreq L231
2466 0366 L431:
2467 0366 48 sll a
2468 0367 5a decw x
2469 0368 26fc jrne L431
2470 036a L231:
2471 036a 43 cpl a
2472 036b c4540d and a,21517
2473 036e c7540d ld 21517,a
2475 0371 2021 jra L7211
2476 0373 L3311:
2477 ; 796 ADC1->AWSRH &= (u8)(~((u8)1 << (temp - 8)));
2479 0373 7b01 ld a,(OFST+0,sp)
2480 0375 a008 sub a,#8
2481 0377 5f clrw x
2482 0378 97 ld xl,a
2483 0379 a601 ld a,#1
2484 037b 5d tnzw x
2485 037c 2704 jreq L631
2486 037e L041:
2487 037e 48 sll a
2488 037f 5a decw x
2489 0380 26fc jrne L041
2490 0382 L631:
2491 0382 43 cpl a
2492 0383 c4540c and a,21516
2493 0386 c7540c ld 21516,a
2494 0389 2009 jra L7211
2495 038b L1311:
2496 ; 801 ADC1->CSR &= (u8) (~Flag);
2498 038b 7b02 ld a,(OFST+1,sp)
2499 038d 43 cpl a
2500 038e c45400 and a,21504
2501 0391 c75400 ld 21504,a
2502 0394 L7211:
2503 ; 803 }
2506 0394 85 popw x
2507 0395 81 ret
2560 ; 833 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit)
2560 ; 834 {
2561 switch .text
2562 0396 _ADC1_GetITStatus:
2564 0396 89 pushw x
2565 0397 88 push a
2566 00000001 OFST: set 1
2569 ; 835 ITStatus itstatus = RESET;
2571 ; 836 u8 temp = 0;
2573 ; 839 assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
2575 ; 841 if ((ITPendingBit & 0xF0) == 0x10)
2577 0398 01 rrwa x,a
2578 0399 a4f0 and a,#240
2579 039b 5f clrw x
2580 039c 02 rlwa x,a
2581 039d a30010 cpw x,#16
2582 03a0 2636 jrne L5611
2583 ; 844 temp = (u8)(ITPendingBit & 0x0F);
2585 03a2 7b03 ld a,(OFST+2,sp)
2586 03a4 a40f and a,#15
2587 03a6 6b01 ld (OFST+0,sp),a
2588 ; 845 if (temp < 8)
2590 03a8 7b01 ld a,(OFST+0,sp)
2591 03aa a108 cp a,#8
2592 03ac 2414 jruge L7611
2593 ; 847 itstatus = (u8)(ADC1->AWSRL & (u8)((u8)1 << temp));
2595 03ae 7b01 ld a,(OFST+0,sp)
2596 03b0 5f clrw x
2597 03b1 97 ld xl,a
2598 03b2 a601 ld a,#1
2599 03b4 5d tnzw x
2600 03b5 2704 jreq L441
2601 03b7 L641:
2602 03b7 48 sll a
2603 03b8 5a decw x
2604 03b9 26fc jrne L641
2605 03bb L441:
2606 03bb c4540d and a,21517
2607 03be 6b01 ld (OFST+0,sp),a
2609 03c0 201d jra L3711
2610 03c2 L7611:
2611 ; 851 itstatus = (u8)(ADC1->AWSRH & (u8)((u8)1 << (temp - 8)));
2613 03c2 7b01 ld a,(OFST+0,sp)
2614 03c4 a008 sub a,#8
2615 03c6 5f clrw x
2616 03c7 97 ld xl,a
2617 03c8 a601 ld a,#1
2618 03ca 5d tnzw x
2619 03cb 2704 jreq L051
2620 03cd L251:
2621 03cd 48 sll a
2622 03ce 5a decw x
2623 03cf 26fc jrne L251
2624 03d1 L051:
2625 03d1 c4540c and a,21516
2626 03d4 6b01 ld (OFST+0,sp),a
2627 03d6 2007 jra L3711
2628 03d8 L5611:
2629 ; 856 itstatus = (u8)(ADC1->CSR & ITPendingBit);
2631 03d8 c65400 ld a,21504
2632 03db 1403 and a,(OFST+2,sp)
2633 03dd 6b01 ld (OFST+0,sp),a
2634 03df L3711:
2635 ; 858 return ((ITStatus)itstatus);
2637 03df 7b01 ld a,(OFST+0,sp)
2640 03e1 5b03 addw sp,#3
2641 03e3 81 ret
2684 ; 889 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit)
2684 ; 890 {
2685 switch .text
2686 03e4 _ADC1_ClearITPendingBit:
2688 03e4 89 pushw x
2689 03e5 88 push a
2690 00000001 OFST: set 1
2693 ; 891 u8 temp = 0;
2695 ; 894 assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
2697 ; 896 if ((ITPendingBit& 0xF0) == 0x10)
2699 03e6 01 rrwa x,a
2700 03e7 a4f0 and a,#240
2701 03e9 5f clrw x
2702 03ea 02 rlwa x,a
2703 03eb a30010 cpw x,#16
2704 03ee 263a jrne L5121
2705 ; 899 temp = (u8)(ITPendingBit & 0x0F);
2707 03f0 7b03 ld a,(OFST+2,sp)
2708 03f2 a40f and a,#15
2709 03f4 6b01 ld (OFST+0,sp),a
2710 ; 900 if (temp < 8)
2712 03f6 7b01 ld a,(OFST+0,sp)
2713 03f8 a108 cp a,#8
2714 03fa 2416 jruge L7121
2715 ; 902 ADC1->AWSRL &= (u8)(~((u8)1 << temp));
2717 03fc 7b01 ld a,(OFST+0,sp)
2718 03fe 5f clrw x
2719 03ff 97 ld xl,a
2720 0400 a601 ld a,#1
2721 0402 5d tnzw x
2722 0403 2704 jreq L651
2723 0405 L061:
2724 0405 48 sll a
2725 0406 5a decw x
2726 0407 26fc jrne L061
2727 0409 L651:
2728 0409 43 cpl a
2729 040a c4540d and a,21517
2730 040d c7540d ld 21517,a
2732 0410 2021 jra L3221
2733 0412 L7121:
2734 ; 906 ADC1->AWSRH &= (u8)(~((u8)1 << (temp - 8)));
2736 0412 7b01 ld a,(OFST+0,sp)
2737 0414 a008 sub a,#8
2738 0416 5f clrw x
2739 0417 97 ld xl,a
2740 0418 a601 ld a,#1
2741 041a 5d tnzw x
2742 041b 2704 jreq L261
2743 041d L461:
2744 041d 48 sll a
2745 041e 5a decw x
2746 041f 26fc jrne L461
2747 0421 L261:
2748 0421 43 cpl a
2749 0422 c4540c and a,21516
2750 0425 c7540c ld 21516,a
2751 0428 2009 jra L3221
2752 042a L5121:
2753 ; 911 ADC1->CSR &= (u8) (~ITPendingBit);
2755 042a 7b03 ld a,(OFST+2,sp)
2756 042c 43 cpl a
2757 042d c45400 and a,21504
2758 0430 c75400 ld 21504,a
2759 0433 L3221:
2760 ; 913 }
2763 0433 5b03 addw sp,#3
2764 0435 81 ret
2777 xdef _ADC1_ClearITPendingBit
2778 xdef _ADC1_GetITStatus
2779 xdef _ADC1_ClearFlag
2780 xdef _ADC1_GetFlagStatus
2781 xdef _ADC1_GetAWDChannelStatus
2782 xdef _ADC1_GetBufferValue
2783 xdef _ADC1_SetLowThreshold
2784 xdef _ADC1_SetHighThreshold
2785 xdef _ADC1_GetConversionValue
2786 xdef _ADC1_StartConversion
2787 xdef _ADC1_AWDChannelConfig
2788 xdef _ADC1_ExternalTriggerConfig
2789 xdef _ADC1_ConversionConfig
2790 xdef _ADC1_SchmittTriggerConfig
2791 xdef _ADC1_PrescalerConfig
2792 xdef _ADC1_ITConfig
2793 xdef _ADC1_DataBufferCmd
2794 xdef _ADC1_ScanModeCmd
2795 xdef _ADC1_Cmd
2796 xdef _ADC1_Init
2797 xdef _ADC1_DeInit
2816 end
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