📄 stm8s_adc1.ls
字号:
1436 ; 445 {
1437 switch .text
1438 016b _ADC1_ExternalTriggerConfig:
1440 016b 89 pushw x
1441 00000000 OFST: set 0
1444 ; 448 assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));
1446 ; 449 assert_param(IS_FUNCTIONALSTATE_OK(ADC1_ExtTrigState));
1448 ; 452 ADC1->CR2 &= (u8)(~ADC1_CR2_EXTSEL);
1450 016c c65402 ld a,21506
1451 016f a4cf and a,#207
1452 0171 c75402 ld 21506,a
1453 ; 454 if (ADC1_ExtTrigState != DISABLE)
1455 0174 9f ld a,xl
1456 0175 4d tnz a
1457 0176 2706 jreq L506
1458 ; 457 ADC1->CR2 |= (u8)(ADC1_CR2_EXTTRIG);
1460 0178 721c5402 bset 21506,#6
1462 017c 2004 jra L706
1463 017e L506:
1464 ; 462 ADC1->CR2 &= (u8)(~ADC1_CR2_EXTTRIG);
1466 017e 721d5402 bres 21506,#6
1467 0182 L706:
1468 ; 466 ADC1->CR2 |= (u8)(ADC1_ExtTrigger);
1470 0182 c65402 ld a,21506
1471 0185 1a01 or a,(OFST+1,sp)
1472 0187 c75402 ld 21506,a
1473 ; 468 }
1476 018a 85 popw x
1477 018b 81 ret
1501 ; 488 void ADC1_StartConversion(void)
1501 ; 489 {
1502 switch .text
1503 018c _ADC1_StartConversion:
1507 ; 490 ADC1->CR1 |= ADC1_CR1_ADON;
1509 018c 72105401 bset 21505,#0
1510 ; 491 }
1513 0190 81 ret
1553 ; 509 u16 ADC1_GetConversionValue(void)
1553 ; 510 {
1554 switch .text
1555 0191 _ADC1_GetConversionValue:
1557 0191 5205 subw sp,#5
1558 00000005 OFST: set 5
1561 ; 512 u16 temph = 0;
1563 ; 513 u8 templ = 0;
1565 ; 515 if (ADC1->CR2 & ADC1_CR2_ALIGN) /* Right alignment */
1567 0193 c65402 ld a,21506
1568 0196 a508 bcp a,#8
1569 0198 2715 jreq L736
1570 ; 518 templ = ADC1->DRL;
1572 019a c65405 ld a,21509
1573 019d 6b03 ld (OFST-2,sp),a
1574 ; 520 temph = ADC1->DRH;
1576 019f c65404 ld a,21508
1577 01a2 5f clrw x
1578 01a3 97 ld xl,a
1579 01a4 1f04 ldw (OFST-1,sp),x
1580 ; 522 temph = (u16)(templ | (u16)(temph << (u8)8));
1582 01a6 1e04 ldw x,(OFST-1,sp)
1583 01a8 7b03 ld a,(OFST-2,sp)
1584 01aa 02 rlwa x,a
1585 01ab 1f04 ldw (OFST-1,sp),x
1587 01ad 2021 jra L146
1588 01af L736:
1589 ; 527 temph = ADC1->DRH;
1591 01af c65404 ld a,21508
1592 01b2 5f clrw x
1593 01b3 97 ld xl,a
1594 01b4 1f04 ldw (OFST-1,sp),x
1595 ; 529 templ = ADC1->DRL;
1597 01b6 c65405 ld a,21509
1598 01b9 6b03 ld (OFST-2,sp),a
1599 ; 531 temph = (u16)((u16)(templ << (u8)6) | (u16)(temph << (u8)8));
1601 01bb 1e04 ldw x,(OFST-1,sp)
1602 01bd 4f clr a
1603 01be 02 rlwa x,a
1604 01bf 1f01 ldw (OFST-4,sp),x
1605 01c1 7b03 ld a,(OFST-2,sp)
1606 01c3 97 ld xl,a
1607 01c4 a640 ld a,#64
1608 01c6 42 mul x,a
1609 01c7 01 rrwa x,a
1610 01c8 1a02 or a,(OFST-3,sp)
1611 01ca 01 rrwa x,a
1612 01cb 1a01 or a,(OFST-4,sp)
1613 01cd 01 rrwa x,a
1614 01ce 1f04 ldw (OFST-1,sp),x
1615 01d0 L146:
1616 ; 534 return ((u16)temph);
1618 01d0 1e04 ldw x,(OFST-1,sp)
1621 01d2 5b05 addw sp,#5
1622 01d4 81 ret
1668 ; 555 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState)
1668 ; 556 {
1669 switch .text
1670 01d5 _ADC1_AWDChannelConfig:
1672 01d5 89 pushw x
1673 00000000 OFST: set 0
1676 ; 558 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1678 ; 559 assert_param(IS_ADC1_CHANNEL_OK(Channel));
1680 ; 561 if (Channel < (u8)8)
1682 01d6 9e ld a,xh
1683 01d7 a108 cp a,#8
1684 01d9 242e jruge L566
1685 ; 563 if (NewState != DISABLE)
1687 01db 9f ld a,xl
1688 01dc 4d tnz a
1689 01dd 2714 jreq L766
1690 ; 565 ADC1->AWCRL |= (u8)((u8)1 << Channel);
1692 01df 9e ld a,xh
1693 01e0 5f clrw x
1694 01e1 97 ld xl,a
1695 01e2 a601 ld a,#1
1696 01e4 5d tnzw x
1697 01e5 2704 jreq L65
1698 01e7 L06:
1699 01e7 48 sll a
1700 01e8 5a decw x
1701 01e9 26fc jrne L06
1702 01eb L65:
1703 01eb ca540f or a,21519
1704 01ee c7540f ld 21519,a
1706 01f1 2047 jra L376
1707 01f3 L766:
1708 ; 569 ADC1->AWCRL &= (u8)(~((u8)1 << Channel));
1710 01f3 7b01 ld a,(OFST+1,sp)
1711 01f5 5f clrw x
1712 01f6 97 ld xl,a
1713 01f7 a601 ld a,#1
1714 01f9 5d tnzw x
1715 01fa 2704 jreq L26
1716 01fc L46:
1717 01fc 48 sll a
1718 01fd 5a decw x
1719 01fe 26fc jrne L46
1720 0200 L26:
1721 0200 43 cpl a
1722 0201 c4540f and a,21519
1723 0204 c7540f ld 21519,a
1724 0207 2031 jra L376
1725 0209 L566:
1726 ; 574 if (NewState != DISABLE)
1728 0209 0d02 tnz (OFST+2,sp)
1729 020b 2717 jreq L576
1730 ; 576 ADC1->AWCRH |= (u8)((u8)1 << (Channel - (u8)8));
1732 020d 7b01 ld a,(OFST+1,sp)
1733 020f a008 sub a,#8
1734 0211 5f clrw x
1735 0212 97 ld xl,a
1736 0213 a601 ld a,#1
1737 0215 5d tnzw x
1738 0216 2704 jreq L66
1739 0218 L07:
1740 0218 48 sll a
1741 0219 5a decw x
1742 021a 26fc jrne L07
1743 021c L66:
1744 021c ca540e or a,21518
1745 021f c7540e ld 21518,a
1747 0222 2016 jra L376
1748 0224 L576:
1749 ; 580 ADC1->AWCRH &= (u8)(~((u8)1 << (Channel - (u8)8)));
1751 0224 7b01 ld a,(OFST+1,sp)
1752 0226 a008 sub a,#8
1753 0228 5f clrw x
1754 0229 97 ld xl,a
1755 022a a601 ld a,#1
1756 022c 5d tnzw x
1757 022d 2704 jreq L27
1758 022f L47:
1759 022f 48 sll a
1760 0230 5a decw x
1761 0231 26fc jrne L47
1762 0233 L27:
1763 0233 43 cpl a
1764 0234 c4540e and a,21518
1765 0237 c7540e ld 21518,a
1766 023a L376:
1767 ; 583 }
1770 023a 85 popw x
1771 023b 81 ret
1804 ; 600 void ADC1_SetHighThreshold(u16 Threshold)
1804 ; 601 {
1805 switch .text
1806 023c _ADC1_SetHighThreshold:
1808 023c 89 pushw x
1809 00000000 OFST: set 0
1812 ; 602 ADC1->HTRH = (u8)(Threshold >> (u8)2);
1814 023d 54 srlw x
1815 023e 54 srlw x
1816 023f 9f ld a,xl
1817 0240 c75408 ld 21512,a
1818 ; 603 ADC1->HTRL = (u8)Threshold;
1820 0243 7b02 ld a,(OFST+2,sp)
1821 0245 c75409 ld 21513,a
1822 ; 604 }
1825 0248 85 popw x
1826 0249 81 ret
1859 ; 621 void ADC1_SetLowThreshold(u16 Threshold)
1859 ; 622 {
1860 switch .text
1861 024a _ADC1_SetLowThreshold:
1863 024a 89 pushw x
1864 00000000 OFST: set 0
1867 ; 623 ADC1->LTRH = (u8)(Threshold >> (u8)2);
1869 024b 54 srlw x
1870 024c 54 srlw x
1871 024d 9f ld a,xl
1872 024e c7540a ld 21514,a
1873 ; 624 ADC1->LTRL = (u8)Threshold;
1875 0251 7b02 ld a,(OFST+2,sp)
1876 0253 c7540b ld 21515,a
1877 ; 625 }
1880 0256 85 popw x
1881 0257 81 ret
1928 ; 642 u16 ADC1_GetBufferValue(u8 Buffer)
1928 ; 643 {
1929 switch .text
1930 0258 _ADC1_GetBufferValue:
1932 0258 88 push a
1933 0259 5205 subw sp,#5
1934 00000005 OFST: set 5
1937 ; 645 u16 temph = 0;
1939 ; 646 u8 templ = 0;
1941 ; 649 assert_param(IS_ADC1_BUFFER_OK(Buffer));
1943 ; 651 if (ADC1->CR2 & ADC1_CR2_ALIGN) /* Right alignment */
1945 025b c65402 ld a,21506
1946 025e a508 bcp a,#8
1947 0260 271f jreq L157
1948 ; 654 templ = *(u8*)(ADC1_BaseAddress + (Buffer << 1) + 1);
1950 0262 7b06 ld a,(OFST+1,sp)
1951 0264 5f clrw x
1952 0265 97 ld xl,a
1953 0266 58 sllw x
1954 0267 d653e1 ld a,(21473,x)
1955 026a 6b03 ld (OFST-2,sp),a
1956 ; 656 temph = *(u8*)(ADC1_BaseAddress + (Buffer << 1));
1958 026c 7b06 ld a,(OFST+1,sp)
1959 026e 5f clrw x
1960 026f 97 ld xl,a
1961 0270 58 sllw x
1962 0271 d653e0 ld a,(21472,x)
1963 0274 5f clrw x
1964 0275 97 ld xl,a
1965 0276 1f04 ldw (OFST-1,sp),x
1966 ; 658 temph = (u16)(templ | (u16)(temph << (u8)8));
1968 0278 1e04 ldw x,(OFST-1,sp)
1969 027a 7b03 ld a,(OFST-2,sp)
1970 027c 02 rlwa x,a
1971 027d 1f04 ldw (OFST-1,sp),x
1973 027f 202b jra L357
1974 0281 L157:
1975 ; 663 temph = *(u8*)(ADC1_BaseAddress + (Buffer << 1));
1977 0281 7b06 ld a,(OFST+1,sp)
1978 0283 5f clrw x
1979 0284 97 ld xl,a
1980 0285 58 sllw x
1981 0286 d653e0 ld a,(21472,x)
1982 0289 5f clrw x
1983 028a 97 ld xl,a
1984 028b 1f04 ldw (OFST-1,sp),x
1985 ; 665 templ = *(u8*)(ADC1_BaseAddress + (Buffer << 1) + 1);
1987 028d 7b06 ld a,(OFST+1,sp)
1988 028f 5f clrw x
1989 0290 97 ld xl,a
1990 0291 58 sllw x
1991 0292 d653e1 ld a,(21473,x)
1992 0295 6b03 ld (OFST-2,sp),a
1993 ; 667 temph = (u16)((u16)(templ << (u8)6) | (u16)(temph << (u8)8));
1995 0297 1e04 ldw x,(OFST-1,sp)
1996 0299 4f clr a
1997 029a 02 rlwa x,a
1998 029b 1f01 ldw (OFST-4,sp),x
1999 029d 7b03 ld a,(OFST-2,sp)
2000 029f 97 ld xl,a
2001 02a0 a640 ld a,#64
2002 02a2 42 mul x,a
2003 02a3 01 rrwa x,a
2004 02a4 1a02 or a,(OFST-3,sp)
2005 02a6 01 rrwa x,a
2006 02a7 1a01 or a,(OFST-4,sp)
2007 02a9 01 rrwa x,a
2008 02aa 1f04 ldw (OFST-1,sp),x
2009 02ac L357:
2010 ; 670 return ((u16)temph);
2012 02ac 1e04 ldw x,(OFST-1,sp)
2015 02ae 5b06 addw sp,#6
2016 02b0 81 ret
2080 ; 690 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel)
2080 ; 691 {
2081 switch .text
2082 02b1 _ADC1_GetAWDChannelStatus:
2084 02b1 88 push a
2085 02b2 88 push a
2086 00000001 OFST: set 1
2089 ; 692 u8 status = 0;
2091 ; 695 assert_param(IS_ADC1_CHANNEL_OK(Channel));
2093 ; 697 if (Channel < (u8)8)
2095 02b3 a108 cp a,#8
2096 02b5 2412 jruge L5001
2097 ; 699 status = (u8)(ADC1->AWSRL & ((u8)1 << Channel));
2099 02b7 5f clrw x
2100 02b8 97 ld xl,a
2101 02b9 a601 ld a,#1
2102 02bb 5d tnzw x
2103 02bc 2704 jreq L601
2104 02be L011:
2105 02be 48 sll a
2106 02bf 5a decw x
2107 02c0 26fc jrne L011
2108 02c2 L601:
2109 02c2 c4540d and a,21517
2110 02c5 6b01 ld (OFST+0,sp),a
2112 02c7 2014 jra L7001
2113 02c9 L5001:
2114 ; 703 status = (u8)(ADC1->AWSRH & ((u8)1 << (Channel - (u8)8)));
2116 02c9 7b02 ld a,(OFST+1,sp)
2117 02cb a008 sub a,#8
2118 02cd 5f clrw x
2119 02ce 97 ld xl,a
2120 02cf a601 ld a,#1
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