stm8s_map.h

STM8全部资料

#define SPI_CR2_BDOE       ((u8)0x40) /*!< Output enable in bi-directional mode mask */
#define SPI_CR2_CRCEN        ((u8)0x20) /*!< Hardware CRC calculation enable mask */
#define SPI_CR2_CRCNEXT      ((u8)0x10) /*!< Transmit CRC next mask */
#define SPI_CR2_RXONLY       ((u8)0x04) /*!< Receive only mask */
#define SPI_CR2_SSM          ((u8)0x02) /*!< Software slave management mask */
#define SPI_CR2_SSI          ((u8)0x01) /*!< Internal slave select mask */

#define SPI_ICR_TXEI     ((u8)0x80) /*!< Tx buffer empty interrupt enable mask */
#define SPI_ICR_RXEI     ((u8)0x40) /*!< Rx buffer empty interrupt enable mask */
#define SPI_ICR_ERRIE     ((u8)0x20) /*!< Error interrupt enable mask */
#define SPI_ICR_WKIE    ((u8)0x10) /*!< Wake-up interrupt enable mask */

#define SPI_SR_BSY    ((u8)0x80) /*!< Busy flag */
#define SPI_SR_OVR    ((u8)0x40) /*!< Overrun flag */
#define SPI_SR_MODF   ((u8)0x20) /*!< Mode fault */
#define SPI_SR_CRCERR ((u8)0x10) /*!< CRC error flag */
#define SPI_SR_WKUP   ((u8)0x08) /*!< Wake-Up flag */
#define SPI_SR_TXE    ((u8)0x02) /*!< Transmit buffer empty */
#define SPI_SR_RXNE   ((u8)0x01) /*!< Receive buffer not empty */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Single Wire Interface Module (SWIM)
  */
typedef struct SWIM_struct
{
  vu8 CSR; /*!< Control/Status register */
  vu8 DR;  /*!< Data register */
}
SWIM_TypeDef;

/*----------------------------------------------------------------------------*/
/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1)
  */

typedef struct UART1_struct
{
  vu8 SR;   /*!< UART1 status register */
  vu8 DR;   /*!< UART1 data register */
  vu8 BRR1; /*!< UART1 baud rate register */
  vu8 BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
  vu8 CR1;  /*!< UART1 control register 1 */
  vu8 CR2;  /*!< UART1 control register 2 */
  vu8 CR3;  /*!< UART1 control register 3 */
  vu8 CR4;  /*!< UART1 control register 4 */
  vu8 CR5;  /*!< UART1 control register 5 */
  vu8 GTR;  /*!< UART1 guard time register */
  vu8 PSCR; /*!< UART1 prescaler register */
}
UART1_TypeDef;

/** @addtogroup UART1_Registers_Reset_Value
  * @{
  */

#define UART1_SR_RESET_VALUE   ((u8)0xC0)
#define UART1_BRR1_RESET_VALUE ((u8)0x00)
#define UART1_BRR2_RESET_VALUE ((u8)0x00)
#define UART1_CR1_RESET_VALUE  ((u8)0x00)
#define UART1_CR2_RESET_VALUE  ((u8)0x00)
#define UART1_CR3_RESET_VALUE  ((u8)0x00)
#define UART1_CR4_RESET_VALUE  ((u8)0x00)
#define UART1_CR5_RESET_VALUE  ((u8)0x00)
#define UART1_GTR_RESET_VALUE  ((u8)0x00)
#define UART1_PSCR_RESET_VALUE ((u8)0x00)

/**
  * @}
  */

/** @addtogroup UART1_Registers_Bits_Definition
  * @{
  */

#define UART1_SR_TXE   ((u8)0x80) /*!< Transmit Data Register Empty mask */
#define UART1_SR_TC    ((u8)0x40) /*!< Transmission Complete mask */
#define UART1_SR_RXNE  ((u8)0x20) /*!< Read Data Register Not Empty mask */
#define UART1_SR_IDLE  ((u8)0x10) /*!< IDLE line detected mask */
#define UART1_SR_OR   ((u8)0x08) /*!< OverRun error mask */
#define UART1_SR_NF    ((u8)0x04) /*!< Noise Flag mask */
#define UART1_SR_FE    ((u8)0x02) /*!< Framing Error mask */
#define UART1_SR_PE    ((u8)0x01) /*!< Parity Error mask */

#define UART1_BRR1_DIVM  ((u8)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */

#define UART1_BRR2_DIVM  ((u8)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */
#define UART1_BRR2_DIVF  ((u8)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */

#define UART1_CR1_R8      ((u8)0x80) /*!< Receive Data bit 8 */
#define UART1_CR1_T8      ((u8)0x40) /*!< Transmit data bit 8 */
#define UART1_CR1_UARTD   ((u8)0x20) /*!< UART1 Disable (for low power consumption) */
#define UART1_CR1_M       ((u8)0x10) /*!< Word length mask */
#define UART1_CR1_WAKE    ((u8)0x08) /*!< Wake-up method mask */
#define UART1_CR1_PCEN    ((u8)0x04) /*!< Parity Control Enable mask */
#define UART1_CR1_PS      ((u8)0x02) /*!< UART1 Parity Selection */
#define UART1_CR1_PIEN    ((u8)0x01) /*!< UART1 Parity Interrupt Enable mask */

#define UART1_CR2_TIEN    ((u8)0x80) /*!< Transmitter Interrupt Enable mask */
#define UART1_CR2_TCIEN   ((u8)0x40) /*!< TransmissionComplete Interrupt Enable mask */
#define UART1_CR2_RIEN    ((u8)0x20) /*!< Receiver Interrupt Enable mask */
#define UART1_CR2_ILIEN   ((u8)0x10) /*!< IDLE Line Interrupt Enable mask */
#define UART1_CR2_TEN     ((u8)0x08) /*!< Transmitter Enable mask */
#define UART1_CR2_REN     ((u8)0x04) /*!< Receiver Enable mask */
#define UART1_CR2_RWU     ((u8)0x02) /*!< Receiver Wake-Up mask */
#define UART1_CR2_SBK     ((u8)0x01) /*!< Send Break mask */

#define UART1_CR3_LINEN   ((u8)0x40) /*!< Alternate Function outpu mask */
#define UART1_CR3_STOP    ((u8)0x30) /*!< STOP bits [1:0] mask */
#define UART1_CR3_CKEN    ((u8)0x08) /*!< Clock Enable mask */
#define UART1_CR3_CPOL    ((u8)0x04) /*!< Clock Polarity mask */
#define UART1_CR3_CPHA    ((u8)0x02) /*!< Clock Phase mask */
#define UART1_CR3_LBCL    ((u8)0x01) /*!< Last Bit Clock pulse mask */

#define UART1_CR4_LBDIEN  ((u8)0x40) /*!< LIN Break Detection Interrupt Enable mask */
#define UART1_CR4_LBDL    ((u8)0x20) /*!< LIN Break Detection Length mask */
#define UART1_CR4_LBDF    ((u8)0x10) /*!< LIN Break Detection Flag mask */
#define UART1_CR4_ADD     ((u8)0x0F) /*!< Address of the UART1 node mask */

#define UART1_CR5_SCEN    ((u8)0x20) /*!< Smart Card Enable mask */
#define UART1_CR5_NACK    ((u8)0x10) /*!< Smart Card Nack Enable mask */
#define UART1_CR5_HDSEL   ((u8)0x08) /*!< Half-Duplex Selection mask */
#define UART1_CR5_IRLP    ((u8)0x04) /*!< Irda Low Power Selection mask */
#define UART1_CR5_IREN    ((u8)0x02) /*!< Irda Enable mask */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2)
  */

typedef struct UART2_struct
{
  vu8 SR;   /*!< UART1 status register */
  vu8 DR;   /*!< UART1 data register */
  vu8 BRR1; /*!< UART1 baud rate register */
  vu8 BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
  vu8 CR1;  /*!< UART1 control register 1 */
  vu8 CR2;  /*!< UART1 control register 2 */
  vu8 CR3;  /*!< UART1 control register 3 */
  vu8 CR4;  /*!< UART1 control register 4 */
  vu8 CR5;  /*!< UART1 control register 5 */
	vu8 CR6;  /*!< UART1 control register 6 */
  vu8 GTR;  /*!< UART1 guard time register */
  vu8 PSCR; /*!< UART1 prescaler register */
}
UART2_TypeDef;

/** @addtogroup UART2_Registers_Reset_Value
  * @{
  */

#define UART2_SR_RESET_VALUE   ((u8)0xC0)
#define UART2_BRR1_RESET_VALUE ((u8)0x00)
#define UART2_BRR2_RESET_VALUE ((u8)0x00)
#define UART2_CR1_RESET_VALUE  ((u8)0x00)
#define UART2_CR2_RESET_VALUE  ((u8)0x00)
#define UART2_CR3_RESET_VALUE  ((u8)0x00)
#define UART2_CR4_RESET_VALUE  ((u8)0x00)
#define UART2_CR5_RESET_VALUE  ((u8)0x00)
#define UART2_CR6_RESET_VALUE  ((u8)0x00)
#define UART2_GTR_RESET_VALUE  ((u8)0x00)
#define UART2_PSCR_RESET_VALUE ((u8)0x00)

/**
  * @}
  */

/** @addtogroup UART2_Registers_Bits_Definition
  * @{
  */

#define UART2_SR_TXE   ((u8)0x80) /*!< Transmit Data Register Empty mask */
#define UART2_SR_TC    ((u8)0x40) /*!< Transmission Complete mask */
#define UART2_SR_RXNE  ((u8)0x20) /*!< Read Data Register Not Empty mask */
#define UART2_SR_IDLE  ((u8)0x10) /*!< IDLE line detected mask */
#define UART2_SR_OR   ((u8)0x08) /*!< OverRun error mask */
#define UART2_SR_NF    ((u8)0x04) /*!< Noise Flag mask */
#define UART2_SR_FE    ((u8)0x02) /*!< Framing Error mask */
#define UART2_SR_PE    ((u8)0x01) /*!< Parity Error mask */

#define UART2_BRR1_DIVM  ((u8)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */

#define UART2_BRR2_DIVM  ((u8)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */
#define UART2_BRR2_DIVF  ((u8)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */

#define UART2_CR1_R8      ((u8)0x80) /*!< Receive Data bit 8 */
#define UART2_CR1_T8      ((u8)0x40) /*!< Transmit data bit 8 */
#define UART2_CR1_UARTD   ((u8)0x20) /*!< UART2 Disable (for low power consumption) */
#define UART2_CR1_M       ((u8)0x10) /*!< Word length mask */
#define UART2_CR1_WAKE    ((u8)0x08) /*!< Wake-up method mask */
#define UART2_CR1_PCEN    ((u8)0x04) /*!< Parity Control Enable mask */
#define UART2_CR1_PS      ((u8)0x02) /*!< UART2 Parity Selection */
#define UART2_CR1_PIEN    ((u8)0x01) /*!< UART2 Parity Interrupt Enable mask */

#define UART2_CR2_TIEN    ((u8)0x80) /*!< Transmitter Interrupt Enable mask */
#define UART2_CR2_TCIEN   ((u8)0x40) /*!< TransmissionComplete Interrupt Enable mask */
#define UART2_CR2_RIEN    ((u8)0x20) /*!< Receiver Interrupt Enable mask */
#define UART2_CR2_ILIEN   ((u8)0x10) /*!< IDLE Line Interrupt Enable mask */
#define UART2_CR2_TEN     ((u8)0x08) /*!< Transmitter Enable mask */
#define UART2_CR2_REN     ((u8)0x04) /*!< Receiver Enable mask */
#define UART2_CR2_RWU     ((u8)0x02) /*!< Receiver Wake-Up mask */
#define UART2_CR2_SBK     ((u8)0x01) /*!< Send Break mask */

#define UART2_CR3_LINEN   ((u8)0x40) /*!< Alternate Function outpu mask */
#define UART2_CR3_STOP    ((u8)0x30) /*!< STOP bits [1:0] mask */
#define UART2_CR3_CKEN    ((u8)0x08) /*!< Clock Enable mask */
#define UART2_CR3_CPOL    ((u8)0x04) /*!< Clock Polarity mask */
#define UART2_CR3_CPHA    ((u8)0x02) /*!< Clock Phase mask */
#define UART2_CR3_LBCL    ((u8)0x01) /*!< Last Bit Clock pulse mask */

#define UART2_CR4_LBDIEN  ((u8)0x40) /*!< LIN Break Detection Interrupt Enable mask */
#define UART2_CR4_LBDL    ((u8)0x20) /*!< LIN Break Detection Length mask */
#define UART2_CR4_LBDF    ((u8)0x10) /*!< LIN Break Detection Flag mask */
#define UART2_CR4_ADD     ((u8)0x0F) /*!< Address of the UART2 node mask */

#define UART2_CR5_SCEN    ((u8)0x20) /*!< Smart Card Enable mask */
#define UART2_CR5_NACK    ((u8)0x10) /*!< Smart Card Nack Enable mask */
#define UART2_CR5_HDSEL   ((u8)0x08) /*!< Half-Duplex Selection mask */
#define UART2_CR5_IRLP    ((u8)0x04) /*!< Irda Low Power Selection mask */
#define UART2_CR5_IREN    ((u8)0x02) /*!< Irda Enable mask */

#define UART2_CR6_LDUM    ((u8)0x80) /*!< LIN Divider Update Method */
#define UART2_CR6_LSLV    ((u8)0x20) /*!< LIN Slave Enable */
#define UART2_CR6_LASE    ((u8)0x10) /*!< LIN Autosynchronization Enable */
#define UART2_CR6_LHDIEN  ((u8)0x04) /*!< LIN Header Detection Interrupt Enable */
#define UART2_CR6_LHDF    ((u8)0x02) /*!< LIN Header Detection Flag */
#define UART2_CR6_LSF     ((u8)0x01) /*!< LIN Synch Field */

/**
  * @}
  */


/*----------------------------------------------------------------------------*/
/**
  * @brief LIN Universal Asynchronous Receiver Transmitter (UART3)
  */

typedef struct UART3_struct
{
  vu8 SR;       /*!< status register */
  vu8 DR;       /*!< data register */
  vu8 BRR1;     /*!< baud rate register */
  vu8 BRR2;     /*!< DIV mantissa[11:8] SCIDIV fraction */
  vu8 CR1;      /*!< control register 1 */
  vu8 CR2;      /*!< control register 2 */
  vu8 CR3;      /*!< control register 3 */
  vu8 CR4;      /*!< control register 4 */
  vu8 RESERVED; /*!< Reserved byte */
  vu8 CR6;      /*!< control register 5 */
}
UART3_TypeDef;

/** @addtogroup UART3_Registers_Reset_Value
  * @{
  */

#define UART3_SR_RESET_VALUE   ((u8)0xC0)
#define UART3_BRR1_RESET_VALUE ((u8)0x00)
#define UART3_BRR2_RESET_VALUE ((u8)0x00)
#define UART3_CR1_RESET_VALUE  ((u8)0x00)
#define UART3_CR2_RESET_VALUE  ((u8)0x00)
#define UART3_CR3_RESET_VALUE  ((u8)0x00)
#define UART3_CR4_RESET_VALUE  ((u8)0x00)
#define UART3_CR6_RESET_VALUE  ((u8)0x00)

/**
  * @}
  */

/** @addtogroup UART3_Registers_Bits_Definition
  * @{
  */

#define UART3_SR_TXE      ((u8)0x80) /*!< Transmit Data Register Empty mask */
#define UART3_SR_TC       ((u8)0x40) /*!< Transmission Complete mask */
#define UART3_SR_RXNE     ((u8)0x20) /*!< Read Data Register Not Empty mask */
#define UART3_SR_IDLE     ((u8)0x10) /*!< IDLE line detected mask */
#define UART3_SR_OR       ((u8)0x08) /*!< OverRun error mask */
#define UART3_SR_NF       ((u8)0x04) /*!< Noise Flag mask */
#define UART3_SR_FE       ((u8)0x02) /*!< Framing Error mask */
#define UART3_SR_PE       ((u8)0x01) /*!< Parity Error mask */

#define UART3_BRR1_DIVM   ((u8)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */

#define UART3_BRR2_DIVM   ((u8)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */
#define UART3_BRR2_DIVF   ((u8)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */

#define UART3_CR1_R8      ((u8)0x80) /*!< Receive Data bit 8 */
#define UART3_CR1_T8      ((u8)0x40) /*!< Transmit data bit 8 */
#define UART3_CR1_UARTD   ((u8)0x20) /*!< UART Disable (for low power consumption) */
#define UART3_CR1_M       ((u8)0x10) /*!< Word length mask */
#define UART3_CR1_WAKE    ((u8)0x08) /*!< Wake-up method mask */
#define UART3_CR1_PCEN    ((u8)0x04) /*!< Parity control enable mask */
#define UART3_CR1_PS      ((u8)0x02) /*!< Parity selection bit mask */
#define UART3_CR1_PIEN    ((u8)0x01) /*!< Parity interrupt enable bit mask */

#define UART3_CR2_TIEN    ((u8)0x80) /*!< Transmitter Interrupt Enable mask */
#define UART3_CR2_TCIEN   ((u8)0x40) /*!< TransmissionComplete Interrupt Enable mask */
#define UART3_CR2_RIEN    ((u8)0x20) /*!< Receiver Interrupt Enable mask */
#define UART3_CR2_ILIEN   ((u8)0x10) /*!< IDLE Line Interrupt Enable mask */
#define UART3_CR2_TEN     ((u8)0x08) /*!< Transmitter Enable mask */
#define UART3_CR2_REN     ((u8)0x04) /*!< Receiver Enable mask */
#define UART3_CR2_RWU     ((u8)0x02) /*!< Receiver Wake-Up mask */
#define UART3_CR2_SBK     ((u8)0x01) /*!< Send Break mask */

#define UART3_CR3_LINEN   ((u8)0x40) /*!< Alternate Function outpu mask */
#define UART3_CR3_STOP    ((u8)0x30) /*!< STOP bits [1:0] mask */

#define UART3_CR4_LBDIEN  ((u8)0x40) /*!< LIN Break Detection Interrupt Enable mask */
#define UART3_CR4_LBDL    ((u8)0x20) /*!< LIN Break Detection Length mask */
#define UART3_CR4_LBDF    ((u8)0x10) /*!< LIN Break Detection Flag mask */
#define UART3_CR4_ADD     ((u8)0x0F) /*!< Address of the UART3 node mask */

#define UART3_CR6_LDUM    ((u8)0x80) /*!< LIN Divider Update Method */
#define UART3_CR6_LSLV    ((u8)0x20) /*!< LIN Slave Enable */
#define UART3_CR6_LASE    ((u8)0x10) /*!< LIN Autosynchroniz