📄 stm8s.h
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vu8 CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */
vu8 CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */
vu8 CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */
vu8 CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */
vu8 CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */
vu8 CNTRH; /*!<TIM5 Counter High */
vu8 CNTRL; /*!<TIM5 Counter Low */
vu8 PSCR; /*!<TIM5 Prescaler Register */
vu8 ARRH; /*!<TIM5 Auto-Reload Register High */
vu8 ARRL; /*!<TIM5 Auto-Reload Register Low */
vu8 CCR1H; /*!<TIM5 Capture/Compare Register 1 High */
vu8 CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */
vu8 CCR2H; /*!<TIM5 Capture/Compare Register 2 High */
vu8 CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */
vu8 CCR3H; /*!<TIM5 Capture/Compare Register 3 High */
vu8 CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */
}TIM5_TypeDef;
/** @addtogroup TIM5_Registers_Reset_Value
* @{
*/
#define TIM5_CR1_RESET_VALUE ((u8)0x00)
#define TIM5_CR2_RESET_VALUE ((u8)0x00)
#define TIM5_SMCR_RESET_VALUE ((u8)0x00)
#define TIM5_IER_RESET_VALUE ((u8)0x00)
#define TIM5_SR1_RESET_VALUE ((u8)0x00)
#define TIM5_SR2_RESET_VALUE ((u8)0x00)
#define TIM5_EGR_RESET_VALUE ((u8)0x00)
#define TIM5_CCMR1_RESET_VALUE ((u8)0x00)
#define TIM5_CCMR2_RESET_VALUE ((u8)0x00)
#define TIM5_CCMR3_RESET_VALUE ((u8)0x00)
#define TIM5_CCER1_RESET_VALUE ((u8)0x00)
#define TIM5_CCER2_RESET_VALUE ((u8)0x00)
#define TIM5_CNTRH_RESET_VALUE ((u8)0x00)
#define TIM5_CNTRL_RESET_VALUE ((u8)0x00)
#define TIM5_PSCR_RESET_VALUE ((u8)0x00)
#define TIM5_ARRH_RESET_VALUE ((u8)0xFF)
#define TIM5_ARRL_RESET_VALUE ((u8)0xFF)
#define TIM5_CCR1H_RESET_VALUE ((u8)0x00)
#define TIM5_CCR1L_RESET_VALUE ((u8)0x00)
#define TIM5_CCR2H_RESET_VALUE ((u8)0x00)
#define TIM5_CCR2L_RESET_VALUE ((u8)0x00)
#define TIM5_CCR3H_RESET_VALUE ((u8)0x00)
#define TIM5_CCR3L_RESET_VALUE ((u8)0x00)
/**
* @}
*/
/** @addtogroup TIM5_Registers_Bits_Definition
* @{
*/
/* CR1*/
#define TIM5_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */
#define TIM5_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */
#define TIM5_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */
#define TIM5_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */
#define TIM5_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */
/* CR2*/
#define TIM5_CR2_TI1S ((u8)0x80) /*!< TI1S Selection Mask. */
#define TIM5_CR2_MMS ((u8)0x70) /*!< MMS Selection Mask. */
/* SMCR*/
#define TIM5_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode Mask. */
#define TIM5_SMCR_TS ((u8)0x70) /*!< Trigger Selection Mask. */
#define TIM5_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection Mask. */
/*IER*/
#define TIM5_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable mask. */
#define TIM5_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
#define TIM5_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
#define TIM5_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
#define TIM5_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */
/*SR1*/
#define TIM5_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */
#define TIM5_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
#define TIM5_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
#define TIM5_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
#define TIM5_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */
/*SR2*/
#define TIM5_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
#define TIM5_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
#define TIM5_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
/*EGR*/
#define TIM5_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */
#define TIM5_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */
#define TIM5_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */
#define TIM5_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */
#define TIM5_EGR_UG ((u8)0x01) /*!< Update Generation mask. */
/*CCMR*/
#define TIM5_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */
#define TIM5_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */
#define TIM5_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */
#define TIM5_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */
#define TIM5_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */
/*CCER1*/
#define TIM5_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */
#define TIM5_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */
#define TIM5_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */
#define TIM5_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */
/*CCER2*/
#define TIM5_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */
#define TIM5_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */
/*CNTR*/
#define TIM5_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */
#define TIM5_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */
/*PSCR*/
#define TIM5_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */
/*ARR*/
#define TIM5_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */
#define TIM5_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */
/*CCR1*/
#define TIM5_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
#define TIM5_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
/*CCR2*/
#define TIM5_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
#define TIM5_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
/*CCR3*/
#define TIM5_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
#define TIM5_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
/*CCMR*/
#define TIM5_CCMR_TIxDirect_Set ((u8)0x01)
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief 8-bit system timer with synchro module(TIM6)
*/
typedef struct TIM6_struct
{
vu8 CR1; /*!< control register 1 */
vu8 CR2; /*!< control register 2 */
vu8 SMCR; /*!< Synchro mode control register */
vu8 IER; /*!< interrupt enable register */
vu8 SR1; /*!< status register 1 */
vu8 EGR; /*!< event generation register */
vu8 CNTR; /*!< counter register */
vu8 PSCR; /*!< prescaler register */
vu8 ARR; /*!< auto-reload register */
}
TIM6_TypeDef;
/** @addtogroup TIM6_Registers_Reset_Value
* @{
*/
#define TIM6_CR1_RESET_VALUE ((u8)0x00)
#define TIM6_CR2_RESET_VALUE ((u8)0x00)
#define TIM6_SMCR_RESET_VALUE ((u8)0x00)
#define TIM6_IER_RESET_VALUE ((u8)0x00)
#define TIM6_SR1_RESET_VALUE ((u8)0x00)
#define TIM6_EGR_RESET_VALUE ((u8)0x00)
#define TIM6_CNTR_RESET_VALUE ((u8)0x00)
#define TIM6_PSCR_RESET_VALUE ((u8)0x00)
#define TIM6_ARR_RESET_VALUE ((u8)0xFF)
/**
* @}
*/
/** @addtogroup TIM6_Registers_Bits_Definition
* @{
*/
/* CR1*/
#define TIM6_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable Mask. */
#define TIM6_CR1_OPM ((u8)0x08) /*!< One Pulse Mode Mask. */
#define TIM6_CR1_URS ((u8)0x04) /*!< Update Request Source Mask. */
#define TIM6_CR1_UDIS ((u8)0x02) /*!< Update DIsable Mask. */
#define TIM6_CR1_CEN ((u8)0x01) /*!< Counter Enable Mask. */
/* CR2*/
#define TIM6_CR2_MMS ((u8)0x70) /*!< MMS Selection Mask. */
/* SMCR*/
#define TIM6_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode Mask. */
#define TIM6_SMCR_TS ((u8)0x70) /*!< Trigger Selection Mask. */
#define TIM6_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection Mask. */
/* IER*/
#define TIM6_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable Mask. */
#define TIM6_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable Mask. */
/* SR1*/
#define TIM6_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */
#define TIM6_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag Mask. */
/* EGR*/
#define TIM6_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */
#define TIM6_EGR_UG ((u8)0x01) /*!< Update Generation Mask. */
/* CNTR*/
#define TIM6_CNTR_CNT ((u8)0xFF) /*!<Counter Value (LSB) Mask. */
/* PSCR*/
#define TIM6_PSCR_PSC ((u8)0x07) /*!<Prescaler Value Mask. */
#define TIM6_ARR_ARR ((u8)0xFF) /*!<Autoreload Value Mask. */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Inter-Integrated Circuit (I2C)
*/
typedef struct I2C_struct
{
vu8 CR1; /*!< I2C control register 1 */
vu8 CR2; /*!< I2C control register 2 */
vu8 FREQR; /*!< I2C frequency register */
vu8 OARL; /*!< I2C own address register LSB */
vu8 OARH; /*!< I2C own address register MSB */
vu8 RESERVED1; /*!< Reserved byte */
vu8 DR; /*!< I2C data register */
vu8 SR1; /*!< I2C status register 1 */
vu8 SR2; /*!< I2C status register 2 */
vu8 SR3; /*!< I2C status register 3 */
vu8 ITR; /*!< I2C interrupt register */
vu8 CCRL; /*!< I2C clock control register low */
vu8 CCRH; /*!< I2C clock control register high */
vu8 TRISER; /*!< I2C maximum rise time register */
vu8 RESERVED2; /*!< Reserved byte */
}
I2C_TypeDef;
/** @addtogroup I2C_Registers_Reset_Value
* @{
*/
#define I2C_CR1_RESET_VALUE ((u8)0x00)
#define I2C_CR2_RESET_VALUE ((u8)0x00)
#define I2C_FREQR_RESET_VALUE ((u8)0x00)
#define I2C_OARL_RESET_VALUE ((u8)0x00)
#define I2C_OARH_RESET_VALUE ((u8)0x00)
#define I2C_DR_RESET_VALUE ((u8)0x00)
#define I2C_SR1_RESET_VALUE ((u8)0x00)
#define I2C_SR2_RESET_VALUE ((u8)0x00)
#define I2C_SR3_RESET_VALUE ((u8)0x00)
#define I2C_ITR_RESET_VALUE ((u8)0x00)
#define I2C_CCRL_RESET_VALUE ((u8)0x00)
#define I2C_CCRH_RESET_VALUE ((u8)0x00)
#define I2C_TRISER_RESET_VALUE ((u8)0x02)
/**
* @}
*/
/** @addtogroup I2C_Registers_Bits_Definition
* @{
*/
#define I2C_CR1_NOSTRETCH ((u8)0x80) /*!< Clock Stretching Disable (Slave mode) */
#define I2C_CR1_ENGC ((u8)0x40) /*!< General Call Enable */
#define I2C_CR1_PE ((u8)0x01) /*!< Peripheral Enable */
#define I2C_CR2_SWRST ((u8)0x80) /*!< Software Reset */
#define I2C_CR2_POS ((u8)0x08) /*!< Acknowledge */
#define I2C_CR2_ACK ((u8)0x04) /*!< Acknowledge Enable */
#define I2C_CR2_STOP ((u8)0x02) /*!< Stop Generation */
#define I2C_CR2_START ((u8)0x01) /*!< Start Generation */
#define I2C_FREQR_FREQ ((u8)0x3F) /*!< Peripheral Clock Frequency */
#define I2C_OARL_ADD ((u8)0xFE) /*!< Interface Address bits [7..1] */
#define I2C_OARL_ADD0 ((u8)0x01) /*!< Interface Address bit0 */
#define I2C_OARH_ADDMODE ((u8)0x80) /*!< Addressing Mode (Slave mode) */
#define I2C_OARH_ADDCONF ((u8)0x40) /*!< Address Mode Configuration */
#define I2C_OARH_ADD ((u8)0x06) /*!< Interface Address bits [9..8] */
#define I2C_DR_DR ((u8)0xFF) /*!< Data Register */
#define I2C_SR1_TXE ((u8)0x80) /*!< Data Register Empty (transmitters) */
#define I2C_SR1_RXNE ((u8)0x40) /*!< Data Register not Empty (receivers) */
#define I2C_SR1_STOPF ((u8)0x10) /*!< Stop detection (Slave mode) */
#define I2C_SR1_ADD10 ((u8)0x08) /*!< 10-bit header sent (Master mode) */
#define I2C_SR1_BTF ((u8)0x04) /*!< Byte Transfer Finished */
#define I2C_SR1_ADDR ((u8)0x02) /*!< Address sent (master mode)/matched (slave mode) */
#define I2C_SR1_SB ((u8)0x01) /*!< Start Bit (Master mode) */
#define I2C_SR2_WUFH ((u8)0x20) /*!< Wake-up from Halt */
#define I2C_SR2_OVR ((u8)0x08) /*!< Overrun/Underrun */
#define I2C_SR2_AF ((u8)0x04) /*!< Acknowledge Failure */
#define I2C_SR2_ARLO ((u8)0x02) /*!< Arbitration Lost (master mode) */
#define I2C_SR2_BERR ((u8)0x01) /*!< Bus Error */
#define I2C_SR3_GENCALL ((u8)0x10) /*!< General Call Header (Slave mode) */
#define I2C_SR3_TRA ((u8)0x04) /*!< Transmitter/Receiver */
#define I2C_SR3_BUSY ((u8)0x02) /*!< Bus Busy */
#define I2C_SR3_MSL ((u8)0x01) /*!< Master/Slave */
#define I2C_ITR_ITBUFEN ((u8)0x04) /*!< Buffer Interrupt Enable */
#define I2C_ITR_ITEVTEN ((u8)0x02) /*!< Event Interrupt Enable */
#define I2C_ITR_ITERREN ((u8)0x01) /*!< Error Interrupt Enable */
#define I2C_CCRL_CCR ((u8)0xFF) /*!< Clock Control Register (Master mode) */
#define I2C_CCRH_FS ((u8)0x80) /*!< Master Mode Selection */
#define I2C_CCRH_DUTY ((u8)0x40) /*!< Fast Mode Duty Cycle */
#define I2C_CCRH_CCR ((u8)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
#define I2C_TRISER_TRISE ((u8)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Interrupt Controller (ITC)
*/
typedef struct ITC_struct
{
vu8 ISPR1; /*!< Interrupt Software Priority register 1 */
vu8 ISPR2; /*!< Interrupt Software Priority register 2 */
vu8 ISPR3; /*!< Interrupt Software Priority register 3 */
vu8 ISPR4; /*!< Interrupt Software Priority register 4 */
vu8 ISPR5; /*!< Interrupt Software Priority register 5 */
vu8 ISPR6; /*!< Interrupt Software Priority register 6 */
vu8 ISPR7; /*!< Interrupt Software Priority register 7 */
vu8 ISPR8; /*!< Interrupt Software Priority register 8 */
}
ITC_TypeDef;
/** @addtogroup ITC_Registers_Reset_Value
* @{
*/
#define ITC_SPRX_RESET_VALUE ((u8)0xFF) /*!< Reset value of Software Priority registers */
/**
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