sysibc.h

LoPEC Early Access VxWorks BSP

/* sysIbc.h - IBC register definitions */

/* Copyright 2000 Wind River Systems, Inc. */
/* Copyright 2000 Motorola, Inc. */

/*
modification history
--------------------
01b,31jan00,scb	  add PCI config #define's to address PCI lockup errata
01a,14nov00,djs   file created (defines pulled from mv5100)
*/

/*
Description: Contains structure typedefs and device-specific 
defines for Programable Interrupt Bridge (8259 type) chips.
*/


#ifndef	INCsysIbch
#define	INCsysIbch

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

/* includes */

/* structures */

/* macros */

/* default definitions */

#define PIC_ADRS(base,reg)   (CAST (base+(reg*PIC_REG_ADDR_INTERVAL)))

/* register definitions */

#define PIC_port1(base)	PIC_ADRS(base,0x00)	/* port 1. */
#define PIC_port2(base)	PIC_ADRS(base,0x01)	/* port 2. */

/* alias */

#define PIC_IMASK(base)	PIC_port2(base)		/* Interrupt mask. */
#define PIC_IACK(base)	PIC_port1(base)		/* Interrupt acknowledge. */

#define PIC_ISR_MASK(base) PIC_port1(base)	/* in-service register mask */
#define PIC_IRR_MASK(base) PIC_port1(base) 	/* interrupt request reg */

/* 
 * PCI Config Header register definitions
 */

#define SL82565_PCI_CFG_PCI_CTL 	0x40	/* Offset to PCI control reg */
#define SL82565_PCI_CTL_RETRYE		0x02	/* PCI control RETRYE bit */

/*
 *	Non-PCI Config Header register definitions
 *
 *	These are mapped to ISA I/O Space
 */

#define SL82565_INT1_CTRL        (ISA_MSTR_IO_LOCAL + 0x0020)	/* PIC1 */
#define SL82565_INT1_MASK        (ISA_MSTR_IO_LOCAL + 0x0021)
#define SL82565_INT1_ELC         (ISA_MSTR_IO_LOCAL + 0x04d0)
#define SL82565_INT2_CTRL        (ISA_MSTR_IO_LOCAL + 0x00a0)	/* PIC2 */
#define SL82565_INT2_MASK        (ISA_MSTR_IO_LOCAL + 0x00a1)
#define SL82565_INT2_ELC         (ISA_MSTR_IO_LOCAL + 0x04d1)
#define SL82565_TMR1_CNT0        (ISA_MSTR_IO_LOCAL + 0x0040)
#define SL82565_TMR1_CNT1        (ISA_MSTR_IO_LOCAL + 0x0041)
#define SL82565_TMR1_CNT2        (ISA_MSTR_IO_LOCAL + 0x0042)
#define SL82565_TMR1_CMOD        (ISA_MSTR_IO_LOCAL + 0x0043)
#define SL82565_RST_IRQ12        (ISA_MSTR_IO_LOCAL + 0x0060)
#define SL82565_NMI_SCTRL        (ISA_MSTR_IO_LOCAL + 0x0061)
#define SL82565_PCOP             (ISA_MSTR_IO_LOCAL + 0x0c04)
#define SL82565_TMCP             (ISA_MSTR_IO_LOCAL + 0x0c01)

/* programmable interrupt controller (PIC) */

#define PIC1_BASE_ADR           SL82565_INT1_CTRL
#define PIC2_BASE_ADR           SL82565_INT2_CTRL

#define PIC_OCW3_SEL         0x08      /* Select OCW3 */
#define PIC_IRR_READ         0x02      /* Read IRR (Int. req. reg.) */
#define PIC_ISR_READ         0x03      /* Read ISR (In service reg.) */

#ifdef __cplusplus
    }
#endif /* __cplusplus */

#endif	/* INCsysIbch */