syslib.c

LoPEC Early Access VxWorks BSP

/* sysLib.c - Motorola LoPEC board series system-dependent library */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01q,27feb01,cak  Added RTC and Failsafe timer support.
01p,22feb01,scb  Removed commentary references to "universe".
01o,16feb01,scb  Added "guarded" attribute to I/O spaces in sysPhysMemDesc[].
01n,08feb01,cak  Modified comments for serial channels 
01m,05feb01,cak  Added sysOut16, sysIn16, sysOut32, sysIn32 for SCSI support.
01l,31jan01,scb  Winbond PCI lockup errata.
01k,26jan01,scb  L2 cache support.
01j,22jan01,scb  Cleaned up PCI configuration items.
01i,04jan01,scb  Turn off fail-led with macro.
01h,18dec00,cak  Added IDE/ATA support
01g,13dec00,djs  Cleanup/rename macros
01f,08dec00,djs  use VPD when displaying sysModel info.
01e,30nov00,djs  support for i82559
01d,20nov00,scb  Non-romInit.s processor support
01c,17nov00,djs  add IBC support
01b,14nov00,scb  Changes for "romInit.s" processor support
01a,02nov00,djs  created from 01t,15jun00,dmw mv2100/sysLib.c
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c - Intel 8250 UART driver 
    ppcDecTimer.c - PowerPC decrementer timer library (system clock)
    byteNvRam.c - byte-oriented generic non-volatile RAM library
    pciConfigLib.c - PCI configuration library
    mpc107Epic.c - Interrupt Controller
    sysI2cDrv.c - I2C interface driver
    sym895Lib.obj - SYM53C895A PCI to Ultra2 SCSI controller driver
    m48t37.c - STMicroelectronics M48T37 Timekeeper SRAM driver

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "dec21x40End.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"
#include "mpc107MemParam.h"
#include "sysIbc.h"
#include "sysMotVpd.h"

/* defines */

#define ZERO	0


/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: PowerPC Programming Reference, 7-25, 7.4.1]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {

    /* Vector Table and Interrupt Stack */

    {
    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Local DRAM */

    {
    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Access to PCI ISA Legacy space and 16-bit I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI I/O space (32-bit I/O space) */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI memory space (non-prefetchable) */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI memory space (prefetchable) */

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* MCP107 registers */

    {
    (void *) MPC107_EUMB_BASE,
    (void *) MPC107_EUMB_BASE,
    MPC107_EUMB_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* PCI interrupt acknowledge */

    {
    (void *) PCI_MSTR_IACK_WNDW_ADRS,
    (void *) PCI_MSTR_IACK_WNDW_ADRS,
    PCI_MSTR_IACK_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* PCI Configuration Address Register */

    {
    (void *) PCI_MSTR_CONFIG_ADDR_BASE,
    (void *) PCI_MSTR_CONFIG_ADDR_BASE,
    PCI_MSTR_CONFIG_ADDR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* PCI Configuration Data Register */

    {
    (void *) PCI_MSTR_CONFIG_DATA_BASE,
    (void *) PCI_MSTR_CONFIG_DATA_BASE,
    PCI_MSTR_CONFIG_DATA_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Flash base address */

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int    sysBus	   = BUS_TYPE_PCI;	/* system bus type */
int    sysCpu      = CPU;		/* system CPU type (PPC604) */
char * sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int    sysProcNum  = 0;			/* processor number of this CPU */
int    sysFlags;			/* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
UINT   sysVectorIRQ0  = INT_VEC_IRQ0;	/* vector for IRQ0 */

/* last 5 nibbles are board specific, initialized in sysHwInit */

unsigned char clearWd [1]  = { 0x00 };

#ifdef INCLUDE_ATA

ATA_RESOURCE   ataResources[ATA_MAX_CTRLS];

/*
 *  The first member in the ATA_TYPE struct has a dual purpose.
 *  1) If cylinders == 0, the device location is not probed at startup.
 *  2) If cylinders != 0, the device location is probed, and if a device
 *     is found, the driver will fill in the first 3 members of the struct
 *     with the number of cylinders, number of heads, and sectors per track.
 *
 *  The last 2 members of the struct are static and should not be changed.
 *
 *  The ATA_TYPE struct has the following layout:
 *      int cylinders;
 *      int heads;
 *      int sectorsTrack;
 *      int bytesSector;
 *      int precomp;
 *
 *  Note:   If configType == ATA_GEO_FORCE, the user needs to fill in
 *          values for cylinders, heads, and sectorsTrack.
 */

ATA_TYPE    ataTypes [ATA_MAX_CTRLS][ATA_MAX_DRIVES] =
    {
    {
        {ATA_DEV0_STATE, 0, 0, 512, 0xff},  /* controller 0, drive 0 */
        {ATA_DEV1_STATE, 0, 0, 512, 0xff},  /* controller 0, drive 1 */
    },
    {
        {ATA_DEV2_STATE, 0, 0, 512, 0xff},  /* controller 1, drive 0 */
        {ATA_DEV3_STATE, 0, 0, 512, 0xff},  /* controller 1, drive 1 */
    }
    };
#endif  /* INCLUDE_ATA */

/* locals */

LOCAL char sysModelStr[80];
LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG; 

/* forward declarations */

void	sysSpuriousIntHandler(void);
void	sysCpuCheck (void);
char *  sysPhysMemTop (void);
UCHAR	sysNvRead(ULONG);
void	sysNvWrite(ULONG,UCHAR);
STATUS  sysBusProbe (char *, int, int, char *);
IMPORT UINT sysHid1Get(void);
void	sysDebugMsg(char * str, UINT32  recovery);
STATUS	sysAtuInit();			/* initialize ATU */
UINT 	sysGetBusSpd(void);     	/* system bus speed (in megahertz) */
UINT	sysGetBusSpdHertz(void);	/* system bus speed (in hertz) */
UINT	sysGetMpuSpd(void);     	/* processor speed (in megahertz) */
UINT	sysGetMpuSpdHertz(void);	/* processor speed (in hertz) */
UINT	sysGetPciSpd(void);     	/* pci bus speed (in megahertz) */
UINT	sysGetPciSpdHertz(void);	/* pci bus speed (in hertz) */
void    sysDelay (void);
void    sysOut16(UINT16 *, UINT16);
UINT16  sysIn16(UINT16 *);
UINT32  sysIn32(UINT32 *);
void    sysOut32(UINT32 *, UINT32);
void    vmxExcLoad (void);		/* Load exception vects for VMX */

/* externals */

IMPORT UCHAR  sysInByte (ULONG);
IMPORT void   sysOutByte (ULONG, UCHAR);
IMPORT USHORT sysInWord (ULONG);
IMPORT void   sysOutWord (ULONG, USHORT);
IMPORT ULONG  sysInLong (ULONG);
IMPORT void   sysOutLong (ULONG, ULONG);
IMPORT UINT32 sysPciInLong (UINT32);
IMPORT void   sysPciOutLong (UINT32, UINT32);
IMPORT STATUS pciConfigInLong (int, int, int, int, UINT32 *);
IMPORT STATUS pciConfigOutLong (int, int, int, int, UINT32);
IMPORT STATUS pciConfigInWord (int, int, int, int, UINT16 *);
IMPORT STATUS pciConfigOutWord (int, int, int, int, UINT16);
IMPORT void   sysClkIntCIO (void);
IMPORT STATUS sysMemProbeSup (int length, char * src, char * dest);
IMPORT int    sysProbeExc();
IMPORT VOIDFUNCPTR      smUtilTasClearRtn;
IMPORT void   sysBusRmwEnable(UINT, UINT, UINT, char *);
IMPORT void   sysBusRmwDisable(void);
IMPORT UINT32 sysTimeBaseLGet (void);
IMPORT UCHAR  sysProductStr[];
IMPORT UINT32 sysMemParamConfig();

/* BSP DRIVERS */

#include "pci/pciConfigLib.c"
#ifdef INCLUDE_NETWORK
#   include "./sysNet.c"
#   ifdef INCLUDE_END
#      include "./sysEnd.c"
#   endif /* INCLUDE_END */
#endif /* INCLUDE_NETWORK */

#include "sysSerial.c"
#include "mem/byteNvRam.c"
#include "sysMotVpd.c"
#include "timer/ppcDecTimer.c"		/* PPC603 has on chip timers */

#ifdef INCLUDE_SHOW_ROUTINES
#include "pci/pciConfigShow.c"          /* display of PCI config space */
#include "sysMotVpdShow.c"
#endif