mpc107memparam.c

LoPEC Early Access VxWorks BSP

LOCAL void sysSdramSizeInit
    (
    sramConfigReg *pMemControlReg,	/* ptr to memory control structure */
    UCHAR * spdArray[]			/* ptr to SPD data arrays */
    )
    {
    UCHAR * pData;
    register int bank;          /* Bank index counter */
    int validSpd;               /* SPD Validity flag */
    UINT numDimmBanks;          /* Number of DIMM Banks supported */
    int bankIndex;              /* Index for current bank */
    UINT sdramSize = 0;         /* SDRAM Size for the bank */
    UINT rowBits = 0;           /* Row address bit count for MCCR1 */
    UINT numberRowAddress;      /* Number of row addresses on DIMM */
    UINT numberDeviceBanks;     /* Number of banks on SDRAM device */

    validSpd = FALSE;

    /* Fill the memory interface values with bank data from the SPD devices. */

    for (bank = 0; bank < NUM_SDRAM_BANKS; bank += 2)
        {
        if ((pData = spdArray[bank]) != NULL)
            {
            validSpd = TRUE;

            /*
             * Get the number of DIMM banks supported by this SPD.
             * In general, a memory controller will support up to 2 
             * DIMM Banks for each SPD.  Any number other than 1 or 2 
             * should be considered erroneous and reset to 1 for this 
             * device.
             */

            numDimmBanks = pData[SPD_NUM_DIMMBANKS_INDEX];
            if (numDimmBanks < 1 || numDimmBanks > 2)
                numDimmBanks = 1;

            /* Calculate the size of the Bank. */

            sdramSize = calcBankSize(pData);

            /*
             * Retrieve the row address bit count and the number
             * of logical banks on the SDRAM device, from the device's
             * SPD data. These are used to set the row address bit 
             * count in the Memory Control Configuration Register (MCCR1).
             */

            numberRowAddress = pData[SPD_ROW_ADDR_INDEX];
            numberDeviceBanks = pData[SPD_DEV_BANKS_INDEX];

	    /*
	     * Set the bank enable, start and end addresses,
	     * and extended start and end address for any 
	     * bank with a size greater than Zero. 
	     */

            if (sdramSize) 
                {
		for (bankIndex=0; bankIndex < numDimmBanks; bankIndex++)
		    {
		    pMemControlReg->MBER |= (1 << (bank + bankIndex));

		    if (bank < 4) 
			{
			calcMemAddress (sdramSize, bank + bankIndex, 
		                        &pMemControlReg->MER3_2_1_0, 
	                    		&pMemControlReg->MEER3_2_1_0,	
		                        &pMemControlReg->MSR3_2_1_0,
                                        &pMemControlReg->MSER3_2_1_0,
			                &pMemControlReg->sdramSize);
			}
		    else
			{
			calcMemAddress (sdramSize, (bank - 4) + bankIndex, 
		                        &pMemControlReg->MER7_6_5_4, 
                                        &pMemControlReg->MEER3_2_1_0,
		                        &pMemControlReg->MSR7_6_5_4,
                                        &pMemControlReg->MSER3_2_1_0,
			                &pMemControlReg->sdramSize);
			}

                    /*
                     * Set the row address bit count for this bank
                     * of memory in the MCCR1.
		     *
		     * According to Chapter 4-Page 46 of the MPC107
	 	     * manual the encoding for the row bit address count
		     * for SDRAM configurations is the following:
		     *   00 12 row bits by n column bits by 4 logical banks
		     *      (12 x n x 4) 64 or 128 Mbit device
		     *   01 13 row bits by n column bits by 2 logical banks
 		     *      (13 x n x 2) 64 or 128 Mbit device
		     *   10 13 row bits by n column bits by 4 logical banks
		     *      (13 x n x 4) 256 Mbit device
		     *   11 11 row bits by n column bits by 2 logical banks
		     *      (11 x n x 2) 16 Mbit device
                     */

    	    	    if (numberDeviceBanks == 2)	 /* 2 logical banks */
    	    	   	{
    	    	    	if (numberRowAddress == 0x0B)	    /* 16 Mbit */
    	    	    	    {
    	    	    	    rowBits = 0x3;
    	    	    	    }
    	    	    	else if (numberRowAddress == 0x0D)  /* 64/128 Mbit */
    	    	    	    {
    	    	    	    rowBits = 0x1;
    	    	    	    }
    	    	    	else 
    	    	    	    rowBits = 0x0;		     /* Default */
    	    	    	}
    	    	    else if (numberDeviceBanks == 4)	 /* 4 logical banks */
    	    	    	{
    	    	    	if (numberRowAddress == 0x0C)      /* 64/128 Mbit */
    	    	    	    {
    	    	    	    rowBits = 0x0;
    	    	    	    }
    	    	    	else if (numberRowAddress == 0x0D)  /* 256 Mbit */
    	    	    	    {
    	    	    	    rowBits = 0x2;
    	    	    	    }
    	    	    	else 
    	    	    	    rowBits = 0x0;    	     /* Default */
    	    	    	}
    	    	    else 
    	    	    	rowBits = 0x0;    	    	     /* Default */

    	    	    pMemControlReg->MCCR1 |= (rowBits << 
    	    	    	    	    	      (MPC107_RAM_ROW_BIT_SHIFT
    	    	    	    	    	       * (bank + bankIndex)));
		    }
                } 
            }
        }

    /*
     * Verify a valid total size (non-zero) or at least one valid
     * SPD device was found.  Set MCCR1 to 0 if invalid so that default 
     * memory settings can be used.
     */

    if ((!validSpd) || (pMemControlReg->sdramSize == 0))  
        {
        pMemControlReg->MCCR1 = 0;
        }

    }


/******************************************************************************
*
* sysGetSpdData - read and validate the spd information.
*
* This function reads the contents of the caller specified serial presence
* detect EEPROM and validates the checksum.
*
* RETURNS: OK if the SPD contents are valid, ERROR if not.
*/
STATUS sysGetSpdData
    (
    UCHAR spdAddr,
    UCHAR offset,
    UINT16 dataSize,
    UCHAR *spdData
    )
    {

    if (i2cRead (spdAddr, offset, dataSize, spdData) == OK)
        {

        /*
         * The MPC107 I2C interface is painfully slow (5 secs to read 
         * 256 bytes). Since we only read 31 (SPD_SIZE) bytes of SPD 
         * data, the checksum cannot be validated.  Since this is the
         * case, check for SDRAM.  No other memory types are supported. 
         */

        if (spdData[SPD_MEMORY_TYPE_INDEX] == SPD_TYPE_SDRAM)  
            return (OK);
        else
            return (ERROR);

        }

    return (ERROR);
    }
#endif /* !BYPASS_SPD */


/******************************************************************************
*
* sysMemParamConfig - calculate the proper memory interface init values.
*
* This function reads the serial presence detect EEPROM(s) and calculates the
* proper values for configuring the memory interface.
*
* RETURNS: Size of memory configured.
*/

UINT32 sysMemParamConfig
    (
    sramConfigReg *pMemControlReg	/* register image storage */
    )
    {

#ifndef BYPASS_SPD
    /*
     * note: the SDRAM banks are arranged in pairs with one spd device per
     * bank pair. therefore only the even numbered entries in the spdPtrs
     * array are used.
     */

    UCHAR * spdPtrs[NUM_SDRAM_BANKS];			/* spd buffer ptrs */
    register int spd;					/* Spd index counter */

    UCHAR   spdData[NUM_SDRAM_BANKS / 2 * SPD_SIZE];	/* spd data */
    UCHAR * pBfr = &spdData[0];				/* temp buffer ptr */
#endif

    /* Initialize structure */

    pMemControlReg->MCCR1       = 0;
    pMemControlReg->MCCR2       = 0;
    pMemControlReg->MCCR3       = 0;
    pMemControlReg->MCCR4       = 0;

    pMemControlReg->MSR3_2_1_0  = 0;
    pMemControlReg->MSR7_6_5_4  = 0;

    pMemControlReg->MER3_2_1_0  = 0;
    pMemControlReg->MER7_6_5_4  = 0;

    pMemControlReg->MSER3_2_1_0 = 0;
    pMemControlReg->MSER7_6_5_4 = 0;

    pMemControlReg->MEER3_2_1_0 = 0;
    pMemControlReg->MEER7_6_5_4 = 0;

    pMemControlReg->MPMR        = 0;
    pMemControlReg->MBER        = 0;
    pMemControlReg->sdramSize   = 0;

    /* Initialize the I2C interface. */

    if (i2cDrvInit(I2C_DRV_TYPE) == ERROR)
        {
        return (0); 
        }

#ifndef BYPASS_SPD
    /* Loop through each spd device */

    for (spd = 0; spd < NUM_SDRAM_BANKS; spd +=2)
        {
        spdPtrs[spd] = NULL;

        /* Read the spd data into the current buffer and validate */

        if (sysGetSpdData (SPD_EEPROM_ADRS0 + spd, 0, SPD_SIZE, pBfr) == OK)
            {
            /* Save current buffer address and advance to the next buffer */

            spdPtrs[spd] = pBfr;
            pBfr += SPD_SIZE;

            }
        }

    /* Calculate the memory controller initialization parameters */

    sysSdramSpeedInit (pMemControlReg, &spdPtrs[0]);
    sysSdramSizeInit (pMemControlReg, &spdPtrs[0]);

    return (pMemControlReg->sdramSize);

#else

    return (LOCAL_MEM_SIZE);

#endif /* !BYPASS_SPD */

    }

/******************************************************************************
*
* flashFailLed - debug function to flash the FAIL led.
*
* This routine flashes a pattern (short and long illuminations) on the
* fail LED.  The 'pattern' parameter contains a bit pattern of length
* 'patternLength' which will be flashed on the fail LED.  The 'hang'
* parameter, when TRUE will cause the pattern to be flashed forever in
* a loop.  If 'hang' is false, it will flash the pattern only once.
* For example if 'pattern' is 0xCD (11001101b) and patternLength is 8 then
* 8 flashes will be displayed in the following order: long, short, long
* long, short, short, long, long.  The flasing pattern can be interpreted
* as a starting with the low order bit of the 'pattern' and proceeding
* to the high order bit of the pattern for 'patternLength' bits.  A
* 0 will be displayed as a short flash and a 1 will be displayed as a
* long flash.
*
* RETURNS: N/A
*/

void flashFailLed
    (
    BOOL   hang,  	  /* Flash forever is this variable is true  */
    UINT32 pattern,	  /* Bit pattern to flash */ 
    int    patternLength  /* Length of bit pattern to flash */
    )
    {
    int modulus = 0;

    FAIL_LED_OFF;
    do  {
	if ( (pattern & (1 << modulus)) != 0)
	    {
	    FAIL_LED_ON;
            MS_DELAY(700);	/* long flash */
	    FAIL_LED_OFF;
	    MS_DELAY(300);
	    }
        else
	    {
	    FAIL_LED_ON;
            MS_DELAY(50);	/* short flash */
	    FAIL_LED_OFF;
	    MS_DELAY(500);
	    }
        modulus = ((modulus + 1) % patternLength);
	if (modulus == 0)
	    MS_DELAY(3000);	/* 3-sec delay between patterns */
	} while (hang == TRUE);
    }