mpc107memparam.c

LoPEC Early Access VxWorks BSP

                sdramDimmType = spdValue; 
                }
            }
    	}

    /* 
     * RMW Parity Error Detection or ECC
     *
     * If a DIMM type 0 is detected, configure the MPC107 for
     * registered, no parity or ECC mode.
     * If a DIMM type 1 or 2 is detected and INCLUDE_ECC is not 
     * defined configure the MPC107 for inline, RMW parity enabled
     * mode.
     * If a DIMM type 1 or 2 is detected and INCLUDE_ECC is defined
     * configure the MPC107 for inline, ECC enabled mode.
     */ 

    if (sdramDimmType == 1 || sdramDimmType == 2)
    	{
#ifdef INCLUDE_ECC
    	pMemControlReg->MCCR2 |= ( MPC107_MCC2_RMW_PAR | 
				   MPC107_MCC2_WR_PAR_CHK_EN |
				   MPC107_MCC2_RD_PARECC_EN );
#else
    	pMemControlReg->MCCR2 |= ( MPC107_MCC2_WR_PAR_CHK_EN | 
				   MPC107_MCC2_RD_PARECC_EN |
				   MPC107_MCC2_PARITY_OR_ECC |
				   MPC107_MCC2_RMW_PAR );
#endif
    	pMemControlReg->MCCR4 |= MPC107_MCC4_INLINE;
    	pMemControlReg->MCCR4 &= ~MPC107_MCC4_REGISTERED;
    	pMemControlReg->ERRENR1 |= MPC107_EE1_MEM_READ_PARITY;
    	} 
    else
    	{
    	pMemControlReg->MCCR4 |= MPC107_MCC4_REGISTERED;
    	}
  
   /*
    * Determine the CAS latency. This is done by taking the supported
    * CAS latency values.  Start with the highest value and check each
    * supported reduced latency value against the minimum cycle time.
    * The CAS latency clock cycle time must be less than the Clock Period.
    * Add 1 to bit, since CAS latency of 1 starts at bit 0.
    */

    if (casLatency != 0xFF)
    	{
        for (Bit = 7; Bit >= 0; Bit--)
	    {
            if (casLatency & (1<<Bit))
    	        {
                sdramTcl = (Bit+1);
                break;
                }
    	    }

    	if (sdramTcl != 0 && tCycReducedCL != 0)
    	    {
            if (casLatency & (1<<(Bit-1)))
    	        {
                if (tCycReducedCL <= clockPeriod)
    	            {
                    sdramTcl -= 1;
                    }
                }
            if (sdramTcl != 0 && tCycReducedCL2 != 0)
    	        {
                if (casLatency & (1<<(Bit-2)))
    	            {
                    if (tCycReducedCL2 <= clockPeriod)
    	                {
                        sdramTcl -= 1;
                        }
                    }
                }
            }
        }

    /*
     * Calculate the timing for the SDRAM Timing Parameter REFREC (tRC).
     * Add the tRAS and tRP timing to get REFREC.
     */

    if (sdramTras && sdramTrp)
    	{
        sdramRefrec = (((sdramTras + sdramTrp) +
                    (clockPeriod - 1)) / clockPeriod);
        if (sdramRefrec < 1 || sdramRefrec > 16)
    	    {
            sdramRefrec = (sdramRefrec < 1 ? 1 : 16);
            }
        }
    else 
    	{
        sdramRefrec = MPC107_MCC3_REFREC_DEFAULT;
        }

    /*
     * REGDIMM defines if the datapath should be configured for registered
     * dimms or not.
     */

    if (sdramAttrib)
    	{
        sdramRegDimm = (sdramAttrib & SPD_ATTR_REGISTERED_MASK) ? 1 : 0;
        }

    /* 
     * RDLAT - 60X Bus Data Latency From Read Command.
     * 
     * RDLAT must be increased by one if the DIMMs are registered, 
     * that is MCCR3[REGDIMM] = 1.  Cas Latency +1 for registered
     * buffer mode (dimmType = 0).  Cas Latency + 2 for inline buffer 
     * mode (dimmType = 1 or 2).  
     * The MPC107 chip supports maximum RDLAT of 6.
     */

    if (sdramRegDimm)
    	lowLimit = 2;
    else 
    	lowLimit = 1;

    if (sdramDimmType == 1 || sdramDimmType == 2)
    	lowLimit += 2;
    else
    	lowLimit += 1;

    /*
     * RDLAT Buffer Mode Delay: 1 = Registered
     *                          2 = In-line ECC
     * RDLAT Delay Due to REGDIMM Value: 0 = Unbuffered DIMM
     *                                   1 = Registered DIMM
     *
     * RDLAT = CAS Latency + buffer mode delay + delay due to REGDIMM value
     */

    sdramDimmType = 0;
    if (pMemControlReg->MCCR4 & MPC107_MCC4_REGISTERED) 
    	sdramDimmType = 1;

    if (pMemControlReg->MCCR4 & MPC107_MCC4_INLINE) 
    	sdramDimmType = 2;

    sdramRdlat = (sdramTcl + sdramRegDimm + sdramDimmType);
    if (sdramRdlat < lowLimit || sdramRdlat > 6)
    	{
        sdramRdlat = (sdramRdlat < lowLimit ? lowLimit : 6);
        }

    /*
     * PRETOACT equals the Minimum Row Precharge Time divided by the
     * clockPeriod. The spec requirement for PRETOACT is 2 or 3 clocks,
     * adjust any value outside of this requirement to the closest spec
     * value.
     */

    if (sdramTrp)
    	{
        sdramPretoact = ((sdramTrp + (clockPeriod - 1)) / clockPeriod);
        if (sdramPretoact < 1 || sdramPretoact > 16)
    	    {
            sdramPretoact = (sdramPretoact < 1 ? 1 : 16);
            }
        }
    else 
    	{
        sdramPretoact = MPC107_MCC4_PRETOACT_DEFAULT;
        }

    /*
     * ACTOPRE equals the Minimum RAS Pulse Width divided by the clockPeriod.
     * The spec requirement for ACTOPRE is 1 to 16 clocks, adjust any value
     * outside of this requirement to the closest spec value.
     */

    if (sdramTras) 
    	{
        sdramActopre = ((sdramTras + (clockPeriod - 1)) / clockPeriod);
        if (sdramActopre < 1 || sdramActopre > 16) 
    	    {
    	    sdramActopre = (sdramActopre < 1 ? 1 : 16);
            }
        }
    else
    	{
        sdramActopre = MPC107_MCC4_ACTOPRE_DEFAULT;
        }

    /*
     * ACTORW equals the Minimum RAS to CAS delay divided by the clockPeriod.
     * The spec requirement for ACTORW is 2 to 16 clocks, 3 to 16 if Inline
     * ECC/Parity enabled.  Adjust any value outside of this requirement to
     * the closest spec value.
     */

    lowLimit = (sdramDimmType > 0 ? 3 : 2);
    if (sdramTrcd)
    	{
        sdramActorw = (((sdramTrcd + (clockPeriod - 1)) / clockPeriod) +
                      (sdramDimmType > 0 ? 1 : 0));
    	if (sdramActorw < lowLimit || sdramActorw > 16)
    	     {
             sdramActorw = (sdramActorw < lowLimit ? lowLimit : 16);
             }
        }
    else
    	{
        sdramActorw = MPC107_MCC4_ACTORW_DEFAULT;
        }
 
    /*
     * Get the Refresh Interval for the memory using the formula:
     *   REFINT = Refresh Rate * busSpeed in Megahertz
     */

    sdramRefInt = (sdramRefRate * pMemControlReg->clkFrequency) / 1000;

    /*
     * Fill the Speed control registers with the speed initialization values.
     */

    pMemControlReg->MCCR1 |=
       ((sdramRefType & MPC107_MCC1_SREN_MASK) << MPC107_MCC1_SREN_SHIFT);

    pMemControlReg->MCCR2 |=
       ((sdramRefInt & MPC107_MCC2_REFINT_MASK) << MPC107_MCC2_REFINT_SHIFT);

    pMemControlReg->MCCR3 |=
       (((sdramRefrec & MPC107_MCC3_REFREC_MASK) << MPC107_MCC3_REFREC_SHIFT) |
       ((sdramRdlat & MPC107_MCC3_RDLAT_MASK) << MPC107_MCC3_RDLAT_SHIFT));

    /*
     * SDMODE register fields include: OPCODE, CAS Latency, Wrap Type, and
     * Wrap Length.  The OPCODE field is not specified and is forced to
     * b'00000' by the MPC107 when the mode register is written. The Wrap
     * Type is required to be sequential on 60X processor-based systems.
     */

    pMemControlReg->MCCR4 |=
    	(((sdramPretoact & MPC107_MCC4_PRETOACT_MASK) << 
    	MPC107_MCC4_PRETOACT_SHIFT) |
        ((sdramActopre & MPC107_MCC4_ACTOPRE_MASK) << 
    	MPC107_MCC4_ACTOPRE_SHIFT) |
        ((sdramRegDimm & MPC107_MCC4_REGDIMM_MASK) <<
        MPC107_MCC4_REGDIMM_SHIFT) |
        ((sdramTcl & MPC107_MCC4_CAS_LAT_MASK) << MPC107_MCC4_SDMODE_CAS_SHF) |
        ((MPC107_MCC4_WRAP_DEFAULT & MPC107_MCC4_WRAP_MASK) << 
    	MPC107_MCC4_SDMODE_SHIFT) | 
       ((sdramActorw & MPC107_MCC4_ACTORW_MASK) << MPC107_MCC4_ACTORW_SHIFT));

    return;

    }


/******************************************************************************
*
* calcBankSize - calculate the size of a sdram bank
*
* This function calculates the size of a sdram bank based on SPD data.
*
* RETURNS: the size of a sdram bank
*/

LOCAL UINT32 calcBankSize
    (
    UCHAR *spdData	/* This bank's SPD data */
    )
    {
    UINT32 bankSize;

    /*
     * Calculate the SDRAM Bank Size using the formula:
     * BankSize = (Total Row Addresses * Total Column Addresses *
     *              Number Device Banks * Data Width in Bytes);
     */

    bankSize = ((1 << spdData[SPD_ROW_ADDR_INDEX]) *
                (1 << spdData[SPD_COL_ADDR_INDEX]) *
                spdData[SPD_DEV_BANKS_INDEX] * 8);

    return (bankSize);

    }


/******************************************************************************
*
* calcMemAddress - calculate the memory bank end and start addresses.
*
* This function calculates the memory bank ending address based on
* the size of the memory, the bank and the existing ending address
* value.  This function also updates the total amount of memory.
*
* RETURNS: N/A
*/

void calcMemAddress
    (
    UINT32 sdramSize,	/* size of this bank */
    UINT32 bank,	/* bank number */
    UINT32 *endAddr,	/* memory ending address */
    UINT32 *eEndAddr,   /* extended memory ending address */
    UINT32 *startAddr,	/* start address for this bank */
    UINT32 *eStartAddr, /* extended memory starting address */
    UINT32 *totalSize	/* running total amount of memory */
    )
    {
    *startAddr |= (((*totalSize >> MPC107_MEM_ADDR_SHIFT) <<
                   (bank * MPC107_MEM_BANK_INDEX)) &
                   (MPC107_MEM_BANK_MASK << (bank * MPC107_MEM_BANK_INDEX)));

    *eStartAddr |= ((*totalSize >> MPC107_EMEM_ADDR_SHIFT) <<
                    (bank * MPC107_MEM_BANK_INDEX));

    *totalSize += sdramSize;

    *endAddr |= ((((*totalSize - 1) >> MPC107_MEM_ADDR_SHIFT) <<
                 (bank * MPC107_MEM_BANK_INDEX)) &
                 (MPC107_MEM_BANK_MASK << (bank * MPC107_MEM_BANK_INDEX)));

    *eEndAddr |= (((*totalSize - 1) >> MPC107_EMEM_ADDR_SHIFT) <<
                  (bank * MPC107_MEM_BANK_INDEX));
    }


/******************************************************************************
*
* sysSdramSizeInit - initialize the SDRAM Size Attributes
*
* This function's purpose is to determine the correct size attributes
* for all banks and to set the ram enable for banks consisting of
* a valid memory configuration.
*
* RETURNS: N/A
*
*/