sym895.h

LoPEC Early Access VxWorks BSP

/* STEST2 SCSI Test Two (RW) */

#define SYM895_STEST2_SCE           0x80 /* SCSI Control Enable */
#define SYM895_STEST2_ROF           0x40 /* Reset SCSI OFfset */
#define SYM895_STEST2_DIF           0x20 /* SCSI Differential Mode */
#define SYM895_STEST2_SLB           0x10 /* SCSI Loopback Mode */
#define SYM895_STEST2_SZM           0x08 /* SCSI High-Impedance Mode */
#define SYM895_STEST2_AWS           0x04 /* Always Wide SCSI */
#define SYM895_STEST2_EXT           0x02 /* Extend SREQ/SACK filtering -  */
                                         /* Should not be set during FAST */
                                         /* SCSI> 5MB/s */
#define SYM895_STEST2_LOW           0x01 /* SCSI LOW level mode; no DMA  */
                                         /* operation occur and no SCRIPTS */ 
                                         /* execute */

/* STEST3 SCSI Test Three (RW) */

#define SYM895_STEST3_TE            0x80 /* Tolerant Enable */ 
#define SYM895_STEST3_STR           0x40 /* SCSI FIFO Test Read */
#define SYM895_STEST3_HSC           0x20 /* Halt Scsi Clock */
#define SYM895_STEST3_DSI           0x10 /* Disable Single Initiator */
                                         /* response (SCSI-1) */
#define SYM895_STEST3_S16           0x08 /* 16-bit System */
#define SYM895_STEST3_TTM           0x04 /* Timer Test Mode */
#define SYM895_STEST3_CSF           0x02 /* Clear Scsi Fifo */
#define SYM895_STEST3_STW           0x01 /* SCSI Fifo Test Write */

/* STEST4 SCSI Test Four (R) */

#define SYM895_STEST4_SMODE_MASK    0xc0 /* SCSI Mode Detect */
#define SYM895_STEST4_LOCK          0x20 /* Detect Clock Quadrupler Lockup */

/* Byte Offsets of On-Chip Registers from the base address */

/* 
 * The registers can be accessed in two ways.One is using Memory IO base addr
 * plus the offset and the other by using PCI config base addr plus offset. 
 * These registers are part of PCI configuration space for the device.
 */

#define MEMIO_REG_BASE      (0x00)
#define PCI_CONFIG_REG_BASE (0x80)
#define BASE                MEMIO_REG_BASE

/* Little Endian offsets */

#define SYM895_OFF_SCNTL0  (BASE)          /* SCTNL0 SCSI control register 0 */
#define SYM895_OFF_SCNTL1  (BASE + 0x01)   /* SCTNL1 SCSI control register 1 */
#define SYM895_OFF_SCNTL2  (BASE + 0x02)   /* SCTNL2 SCSI control register 2 */
#define SYM895_OFF_SCNTL3  (BASE + 0x03)   /* SCTNL3 SCSI control register 3 */
#define SYM895_OFF_SCID    (BASE + 0x04)   /* SCID SCSI chip ID register */
#define SYM895_OFF_SXFER   (BASE + 0x05)   /* SXFER SCSI chip ID register */
#define SYM895_OFF_SDID    (BASE + 0x06)   /* SDID SCSI destination ID  */
#define SYM895_OFF_GPREG   (BASE + 0x07)   /* GPREG General Purpose register */
#define SYM895_OFF_SFBR    (BASE + 0x08)   /* SFBR SCSI first byte received  */
#define SYM895_OFF_SOCL    (BASE + 0x09)   /* SOCL SCSI output control latch */
#define SYM895_OFF_SSID    (BASE + 0x0a)   /* SSID SCSI selector ID */
#define SYM895_OFF_SBCL    (BASE + 0x0b)   /* SBCL SCSI bus control lines */
#define SYM895_OFF_DSTAT   (BASE + 0x0c)   /* DSTAT DMA status register */
#define SYM895_OFF_SSTAT0  (BASE + 0x0d)   /* SSTAT0 SCSI status register 0 */
#define SYM895_OFF_SSTAT1  (BASE + 0x0e)   /* SSTAT1 SCSI status register 0 */
#define SYM895_OFF_SSTAT2  (BASE + 0x0f)   /* SSTAT2 SCSI status register 0 */
#define SYM895_OFF_DSA     (BASE + 0x10)   /* 32-bit DSA data structure */
                                           /* address */
#define SYM895_OFF_ISTAT   (BASE + 0x14)   /* 8-bit ISTAT interrupt status  */
#define SYM895_OFF_CTEST0  (BASE + 0x18)   /* CTEST0 chip test register 0 */
#define SYM895_OFF_CTEST1  (BASE + 0x19)   /* CTEST1 chip test register 1 */
#define SYM895_OFF_CTEST2  (BASE + 0x1a)   /* CTEST2 chip test register 2 */
#define SYM895_OFF_CTEST3  (BASE + 0x1b)   /* CTEST3 chip test register 3 */
#define SYM895_OFF_TEMP    (BASE + 0x1c)   /* 32-bit TEMP temporary holding */
                                           /* register */
#define SYM895_OFF_DFIFO   (BASE + 0x20)   /* DFIFO DMA FIFO control register */
#define SYM895_OFF_CTEST4  (BASE + 0x21)   /* CTEST4 chip test register 4 */
#define SYM895_OFF_CTEST5  (BASE + 0x22)   /* CTEST5 chip test register 5 */
#define SYM895_OFF_CTEST6  (BASE + 0x23)   /* CTEST6 chip test register 6 */
#define SYM895_OFF_DBC     (BASE + 0x24)   /* 24-bit DBC SIOP command reg.*/
#define SYM895_OFF_DCMD    (BASE + 0x27)   /* 8-bit DCMD SIOP command register */
#define SYM895_OFF_DNAD    (BASE + 0x28)   /* 32-bit DNAD DMA buffer ptr */
                                           /* (next addr) */
#define SYM895_OFF_DSP     (BASE + 0x2c)   /* 32-bit DSP SIOP scripts pointer */
                                           /* register */
#define SYM895_OFF_DSPS    (BASE + 0x30)   /* 32-bit DSPS SIOP scripts ptr */
                                           /* save register */
#define SYM895_OFF_DMODE   (BASE + 0x38)   /* DMODE DMA operation mode */
                                           /* register */
#define SYM895_OFF_DIEN    (BASE + 0x39)   /* DIEN DMA interrupt enable */
#define SYM895_OFF_DWT     (BASE + 0x3a)   /* DWT DMA watchdog timer register */
#define SYM895_OFF_DCNTL   (BASE + 0x3b)   /* DCTNL DMA control register */	
#define SYM895_OFF_ADDER   (BASE + 0x3c)   /* 32-bit ADDER Adder output */
                                           /* Register */	
#define SYM895_OFF_SIEN0   (BASE + 0x40)   /* SIEN0 SCSI interrupt enable 0 */
                                           /* register */
#define SYM895_OFF_SIEN1   (BASE + 0x41)   /* SIEN1 SCSI interrupt enable 1 */
                                           /* register */
#define SYM895_OFF_SIST0   (BASE + 0x42)   /* SIST0 SCSI interrupt status 0 */
                                           /* register */
#define SYM895_OFF_SIST1   (BASE + 0x43)   /* SIST1 SCSI interrupt status 1 */
                                           /* register */
#define SYM895_OFF_SLPAR   (BASE + 0x44)   /* SLPAR SCSI longitudinal Parity*/
                                           /* register */
#define SYM895_OFF_SWIDE   (BASE + 0x45)   /* SWIDE SCSI Wide Residue */
#define SYM895_OFF_MACNTL  (BASE + 0x46)   /* MACNTL Memory Access Control */
                                           /* register */
#define SYM895_OFF_GPCNTL  (BASE + 0x47)   /* GPCNTL General Purpose Pin */
                                           /* Control */
#define SYM895_OFF_STIME0  (BASE + 0x48)   /* STIME0 SCSI Timer Zero reg */
#define SYM895_OFF_STIME1  (BASE + 0x49)   /* STIME1 SCSI Timer One reg */
#define SYM895_OFF_RESPID0 (BASE + 0x4a)   /* RESPID Response ID register 0 */
#define SYM895_OFF_RESPID1 (BASE + 0x4b)   /* RESPID Response ID register 1 */
#define SYM895_OFF_STEST0  (BASE + 0x4c)   /* STEST0 SCSI Test 0 register */
#define SYM895_OFF_STEST1  (BASE + 0x4d)   /* STEST1 SCSI Test 1 register */
#define SYM895_OFF_STEST2  (BASE + 0x4e)   /* STEST2 SCSI Test 2 register */
#define SYM895_OFF_STEST3  (BASE + 0x4f)   /* STEST3 SCSI Test 3 register */
#define SYM895_OFF_SIDL    (BASE + 0x50)   /* 16-bit SIDL SCSI input data */
                                           /* latch register */
#define SYM895_OFF_STEST4  (BASE + 0x52)   /* STEST4 SCSI Test 4 register */
#define SYM895_OFF_SODL    (BASE + 0x54)   /* 16-bit SCSI output data latch */
                                           /* register */
#define SYM895_OFF_SBDL    (BASE + 0x58)   /* 16-bit SBDL SCSI bus data lines */
                                           /* register */

#define SYM895_OFF_SCRATCHA0	(BASE + 0x34)	/* SCRATCHA0 gen purpose */
                                                /* scratch register A0 */
#define SYM895_OFF_SCRATCHA1	(BASE + 0x35)	/* SCRATCHA1 gen purpose */ 
                                                /* scratch reg A1 */
#define SYM895_OFF_SCRATCHA2	(BASE + 0x36)	/* SCRATCHA2 gen purpose */
                                                /* scratch reg A2 */
#define SYM895_OFF_SCRATCHA3	(BASE + 0x37)	/* SCRATCHA3 gen purpose */
                                                /* scratch reg A3 */
#define SYM895_OFF_SCRATCHB0	(BASE + 0x5c)	/* SCRATCHB0 gen purpose */
                                                /* scratch reg B0 */
#define SYM895_OFF_SCRATCHB	(BASE + 0x5c)	/* SCRATCHB Scratch Register B */
#define SYM895_OFF_SCRATCHC0	(BASE + 0x60)	/* SCRATCHC Scratch Register C */
#define SYM895_OFF_SCRATCHC1	(BASE + 0x61)	/* SCRATCHC Scratch Register C */
#define SYM895_OFF_SCRATCHC2	(BASE + 0x62)	/* SCRATCHC Scratch Register C */
#define SYM895_OFF_SCRATCHC	(BASE + 0x60)	/* SCRATCHC Scratch Register C */
#define SYM895_OFF_SCRATCHD	(BASE + 0x64)	/* SCRATCHD Scratch Register D */
#define SYM895_OFF_SCRATCHE	(BASE + 0x68)	/* SCRATCHE Scratch Register E */
#define SYM895_OFF_SCRATCHF	(BASE + 0x6c)	/* SCRATCHF Scratch Register F */
#define SYM895_OFF_SCRATCHG	(BASE + 0x70)	/* SCRATCHG Scratch Register G */
#define SYM895_OFF_SCRATCHH	(BASE + 0x74)	/* SCRATCHH Scratch Register H */
#define SYM895_OFF_SCRATCHI	(BASE + 0x78)	/* SCRATCHI Scratch Register I */
#define SYM895_OFF_SCRATCHJ	(BASE + 0x7C)	/* SCRATCHJ Scratch Register J */

/* 
 * The Device Id's (required for finding the device on PCI Bus)
 * for the SYM895 Chip. Note that NCR895 and SYM895 are both the same.
 * the SCSI division of NCR is now Symbios, which is taken over by LSI logic
 */

#define NCR810_DEVICE_ID    0x0001
#define NCR825_DEVICE_ID    0x0003
#define NCR875_DEVICE_ID    0x000f
#define NCR895_DEVICE_ID    0x000c
#define NCR895A_DEVICE_ID   0x0012
#define SYM895_DEVICE_ID    NCR895_DEVICE_ID
#define PCI_ID_SYMBIOS      0x1000

/* 
 * The Block Move Counter Mask.
 * The DBC register in sym895 holds the number of bytes transferred in 
 * a Block Move instruction. It is also used to hold the least significant 
 * 24 bits of the first dword of a SCRIPTS fetch. For more details, please 
 * refer to chap 5, of the 895 data manual.
 * The maximum value that it can store is 0x00ffffff (24 bits only). 
 */

#define SYM895_COUNT_MASK   ((UINT)0x00ffffff)

/* 
 * As a part of the SCSI Thread, the target parameters are to be set
 * in the thread context. These parameters are  encoded. Device (target)id 
 * and a copy of the sxfer register are to be encoded in a single 32 bit word. 
 * Bits 23-16 specify the target bus id(mapped to SDID register) and bits 15-08 
 * specify the copy of sxfer register. Refer to 8-8 of PCI-SCSI Programming 
 * guide.
 */

#define SYM895_TARGET_BUS_ID_SHIFT  16
#define SYM895_XFER_PARAMS_SHIFT    8

/* 
 * Allowable SCSI Synchronous Offset and Transfer period values.
 * Please refer to chap 2, the Functional description and chap 5, Operating 
 * registers of sym895 data manual, for more details.
 */

#define SYM895_MIN_SYNC_OFFSET      1
#define SYM895_MAX_SYNC_OFFSET      31
#define SYM895_ASYNC_OFFSET         0   /* Sync. Offset should be 0x00 */
                                        /* for asynchronous xfers */

/* Allowable values for SCSI Sync. transfer period in XFERP register */

#define SYM895_MIN_XFERP            4
#define SYM895_MAX_XFERP            11  /* Not recommended.see the manual */
#define SYM895_IDEAL_XFERP          4

#define SYM895_SYNC_XFER_PERIOD_SHIFT   5 /* PERIOD is Bits 7-5 of XFER reg */

/* The Value of sxfer register for asynchronous transfers */

#define SYM895_ASYNC_SXFER          0x00

/* 
 * Synchronous Transfer : Clock division factor 
 * Refer to chap 5, Operating Registers, SCNTL3 register bits SCF2-0
 */

#define SYM895_SYNC_MIN_CLK_DIV	    1
#define SYM895_SYNC_MAX_CLK_DIV     7

#define SYM895_SYNC_CLK_DIV_1       1       /* SCLK / 1 */
#define SYM895_SYNC_CLK_DIV_1_5     2       /* SCLK / 1.5 */
#define SYM895_SYNC_CLK_DIV_2       3       /* SCLK / 2 */ 
#define SYM895_SYNC_CLK_DIV_3       4       /* SCLK / 3 */
#define SYM895_SYNC_CLK_DIV_4       5       /* SCLK / 4 */
#define SYM895_SYNC_CLK_DIV_6       6       /* SCLK / 6 */
#define SYM895_SYNC_CLK_DIV_8       7       /* SCLK / 8 */

/* 
 * Asynchronous Transfer : Clock conversion factor 
 * Refer to chap 5, Operating Registers, SCNTL3 register
 * Bits CCF2-0.
 */

#define SYM895_ASYNC_MIN_CLK_DIV    1       /* 16.67 - 25 MHz */
#define SYM895_ASYNC_MAX_CLK_DIV    7       /* 160 MHz : The clock quadrupler  */
                                            /* bit must be set */

/* prescale factor for asynchronous scsi core (scntl3) */

#define SYM895_16MHZ_ASYNC_DIV      0x01    /* 16.67-25.00Mhz input clock */
#define SYM895_25MHZ_ASYNC_DIV      0x02    /* 25.01-37.50Mhz input clock */
#define SYM895_3750MHZ_ASYNC_DIV    0x03    /* 37.51-50.00Mhz input clock */
#define SYM895_50MHZ_ASYNC_DIV      0x04    /* 50.01-75.00Mhz input clock */

/* 
 * Note: 70MHz & 160MHz value has Ultra Enable bit set (b7).
 * When Ultra enable bit is set, the Tolerant Enable bit must also be set . 
 * It is STEST3:TE (bit 7).
 */

#define SYM895_75MHZ_ASYNC_DIV      0x85    /* 75.01-80.00Mhz input clock */

/* 160.00 Mhz input clock with clock quadrupler and 40 Mhz input clock */

#define SYM895_160MHZ_ASYNC_DIV	    0x87    

/* Nano Seconds x 100 clock period */

#define SYM895_1667MHZ      6000    /* 16.67Mhz chip */
#define SYM895_20MHZ        5000    /* 20Mhz chip */
#define SYM895_25MHZ        4000    /* 25Mhz chip */
#define SYM895_3750MHZ      2667    /* 37.50Mhz chip */
#define SYM895_40MHZ        2500    /* 40Mhz chip */
#define SYM895_50MHZ        2000    /* 50Mhz chip */
#define SYM895_66MHZ        1515    /* 66Mhz chip */
#define SYM895_6666MHZ      1500    /* 66Mhz chip */
#define SYM895_75MHZ        1333    /* 75Mhz chip */
#define SYM895_80MHZ        1250    /* 80Mhz chip */
#define SYM895_160MHZ        625    /* 40Mhz chip with Quadrupler */

/* Timer values for General Purpose Timer (STIME1) */

#define SYM895_GEN_DISABLED 0x00    /* Disabled */
#define SYM895_GEN_128MS    0x0B    /* 128 MS */
#define SYM895_GEN_64MS	    0x0A    /* 64 MS */

/* Various Bus Modes supported by 895 */

#define SYM895_BUSMODE_LVD     3
#define SYM895_BUSMODE_SE      2
#define SYM895_BUSMODE_HVD     1

#define SYM895_BUSMODE_SHIFT   6

#define SYM895_MAX_XFER_WIDTH  1    /* in transfer width exponent units.*/
                                    /* 16bits. */

#define SYM895_TYPE     0x895       /* Chip Type; */

/* sym895 PCI Resources  */

#define SYM895_MEMBASE         0xf5200000	
#define SYM895_MEMSIZE         0x00001000      /* memory size for Int.RAM, 4KB */
#define SYM895_RAM_ADR         (SYM895_MEMBASE)
#define SYM895_MEM_ADR         (SYM895_MEMBASE + SYM895_MEMSIZE)
#define SYM895_IO_ADR          0xf800	
#define SYM895_INT_LVL         0x0a
#define SYM895_INIT_STATE_MASK (VM_STATE_MASK_FOR_ALL)
#define SYM895_INIT_STATE      (VM_STATE_FOR_IO)

#define SYM895_DEV_MMU_MSK      (~(VM_PAGE_SIZE - 1))   /* Mask MMU page */
#define SYM895_DEV_ADRS_SIZE    VM_PAGE_SIZE * 2        /* two pages */

/* Controller Options, while creating the Controller Structure */

#define SYM895_ENABLE_PARITY_CHECK      0x01
#define SYM895_ENABLE_SINGLE_STEP       0x02
#define SYM895_COPY_SCRIPTS             0x04

/* SCRIPT ram Size for various controllers */

#define SYM895_SCRIPT_RAM_SIZE 4*1024	/* bytes */

/* Chip register access mode (memory mapped / IO) */

#define SYM895_IO_MAPPED   /* IO mapped access by default */

/* Loopback diagnostics */

#define LOOPBACK_MSG_BYTE  0xa5
#define LOOPBACK_DATA      0x5a5a

/*
 *  Structure , used as an interface between the C Code and the Scripts.
 *  used for storing data in Block Move instructions.
 */

typedef struct moveParams
    {

    ULONG  size;              /* # bytes to move to/from SCSI */

    UINT8 *addr;              /* where in memory they go/come */

    } MOVE_PARAMS;


/*