sym895.h

LoPEC Early Access VxWorks BSP

/* sym895.h - SYM 895 Script SCSI Controller header file */

/* Copyright 1989-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,08feb01,cak  Ported to LoPEC from mv5100 (01a)
*/

#ifndef __INCsym895h
#define __INCsym895h


#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "semLib.h"
#include "scsiLib.h"

/* Bit register definitions for the SYM895 */

/* SCSI Control Zero - SCNTL0 */

#define SYM895_SCNTL0_ARB1     0x80  /* Arbitration Control Bits. */
#define SYM895_SCNTL0_ARB0     0x40  /* define Simple or Full arbitration. */
#define SYM895_SCNTL0_START    0x20  /* Start arbitration sequence */
#define SYM895_SCNTL0_WATN     0x10  /* SATN/signal ctrl on Start sequence */
#define SYM895_SCNTL0_EPC      0x08  /* Parity Check enable */
#define SYM895_SCNTL0_AAP      0x02  /* SATN/ signal control on Parity Error */
#define SYM895_SCNTL0_TRG      0x01  /* Initator/Target mode set */

/* SCSI Control One - SCNTL1 */

#define SYM895_SCNTL1_EXC      0x80  /* Extra Clock Period for data setup */
#define SYM895_SCNTL1_ADB      0x40  /* Asset SCSI Data Bus */
#define SYM895_SCNTL1_DHP      0x20  /* Disable Halt on Parity/ATN (tgt only) */
#define SYM895_SCNTL1_CON      0x10  /* Bus Connection status */
#define SYM895_SCNTL1_RST      0x08  /* Assert RST/ */
#define SYM895_SCNTL1_AESP     0x04  /* Force parity error on SCSI Bus */
#define SYM895_SCNTL1_IARB     0x02  /* Immediate arbitration */
#define SYM895_SCNTL1_SST      0x01  /* Start SCSI transfer */

/* SCNTL2 */

#define SYM895_SCNTL2_SDU      0x80  /* SCSI Disconnect Unexpected */
#define SYM895_SCNTL2_CHM      0x40  /* Chained Move (automatically set/reset)*/
#define SYM895_SCNTL2_SLPMD    0x20  /* Longitudianal parity mode related */
#define SYM895_SCNTL2_SLPHBEN  0x10  /* Longitudianal parity mode related */
#define SYM895_SCNTL2_WSS      0x08  /* Wide SCSI Send */
#define SYM895_SCNTL2_VUE0     0x04  /* Vendor Unique Enhansements related */
#define SYM895_SCNTL2_VUE1     0x02  /* Vendor Unique Enhansements related */
#define SYM895_SCNTL2_WSR      0x01  /* Wide SCSI Receive */
 
/* SCNTL3 */

#define SYM895_SCNTL3_ULTRA    0x80  /* Ultra Enable */
#define SYM895_SCNTL3_SCF_MASK 0x70  /* Syncronous Clock Conv. Factor bits */
#define SYM895_SCNTL3_EWS      0x08  /* Enable WIDE SCSI */
#define SYM895_SCNTL3_CCF_MASK 0x07  /* Clock Conversion Factor bits */

/* SCID */

#define SYM895_SCID_RRE        0x40  /* Enable Response to Reselection */
#define SYM895_SCID_SRE        0x20  /* Enable Response to Selection   */
#define SYM895_SCID_ENC_MASK   0x0f  /* The Encoded SCSI ID mask */

/* SXFER */

#define SYM895_SXFER_XFERP_MASK   0xE0 /* Synchronous transfer period */
#define SYM895_SXFER_OFF_MASK     0x1f /* Sync. Transfer Max. Offset period */

/* SDID */

#define SYM895_SDID_ENC_MASK      0x0f /* The Encoded SCSI ID mask */

/* GPREG */

#define SYM895_GPREG_MASK         0x1f /* Mask for IO pins */
#define SYM895_GPREG_GPIO4        0x10 /* Programmable IO Pin */
#define SYM895_GPREG_GPIO3        0x08 /* Programmable IO Pin */
#define SYM895_GPREG_GPIO2        0x04 /* Programmable IO Pin */
#define SYM895_GPREG_GPIO1        0x02 /* Programmable IO Pin */
#define SYM895_GPREG_GPIO0        0x01 /* Programmable IO Pin */

/* SOCL */

#define SYM895_SOCL_REQ           0x80 /* Assert SCSI REQ/ signal */
#define SYM895_SOCL_ACK           0x40 /* Assert SCSI ACK/ signal */
#define SYM895_SOCL_BSY           0x20 /* Assert SCSI BSY/ signal */
#define SYM895_SOCL_SEL           0x10 /* Assert SCSI SEL/ signal */
#define SYM895_SOCL_ATN           0x08 /* Assert SCSI ATN/ signal */
#define SYM895_SOCL_MSG           0x04 /* Assert SCSI MSG/ signal */
#define SYM895_SOCL_CD            0x02 /* Assert SCSI CD/ signal */
#define SYM895_SOCL_IO            0x01 /* Assert SCSI IO/ signal */

/* SSID */

#define SYM895_SSID_VAL           0x80	 /* SCSI Valid Bit.*/
#define SYM895_SSID_ENC_MASK      0x0f   /* Binary encoded SCSI ID mask 0-15 */

/* SBCL */

#define SYM895_SBCL_REQ           0x80   /* Get  SCSI REQ/ Status */
#define SYM895_SBCL_ACK           0x40   /* Get  SCSI ACK/ Status */
#define SYM895_SBCL_BSY           0x20   /* Get  SCSI BSY/ Status */
#define SYM895_SBCL_SEL           0x10   /* Get  SCSI SEL/ Status */
#define SYM895_SBCL_ATN           0x08   /* Get  SCSI ATN/ Status */
#define SYM895_SBCL_MSG           0x04   /* Get  SCSI MSG/ Status */
#define SYM895_SBCL_CD            0x02   /* Get  SCSI CD/ Status  */
#define SYM895_SBCL_IO            0x01   /* Get  SCSI IO/ Status  */

/* DSTAT (RO) and DIEN (RW enable intr) */

#define SYM895_B_DFE              0x80   /* Dma fifo empty */
#define SYM895_B_MDPE             0x40   /* Master Data Parity Error */
#define SYM895_B_BF               0x20	 /* Bus Fault */
#define SYM895_B_ABT              0x10	 /* Abort condition */
#define SYM895_B_SSI              0x08	 /* Scsi Step Interrupt */
#define SYM895_B_SIR              0x04	 /* Script Interrupt received */
#define SYM895_B_IID              0x01	 /* Illegal Instruction Detected */

/* SSTAT0 */

#define SYM895_SSTAT0_ILF         0x80   /* SIDL Input Latch Full */
#define SYM895_SSTAT0_ORF         0x40   /* SODR Output Register Full */
#define SYM895_SSTAT0_OLF         0x20   /* SODL Output Latch Full */
#define SYM895_SSTAT0_AIP         0x10   /* Arbitration In Progress */ 
#define SYM895_SSTAT0_LOA         0x08   /* LOst Arbitration */
#define SYM895_SSTAT0_WOA         0x04   /* WOn Arbitration */
#define SYM895_SSTAT0_RST         0x02   /* SCSI ReSeT signal in ISTAT reg */
#define SYM895_SSTAT0_SDP0        0x01   /* SCSI SDP/0 parity signal */

/* SSTAT1 RO register */

#define SYM895_SSTAT1_FIFO_MASK   0xf0   /* Also..see the SSTAT2 register */
#define SYM895_SSTAT1_SDP0L       0x08   /* Parity for latched scsi i/p data */
#define SYM895_SSTAT1_MSG         0x04   /* SCSI:MSG Signal, latched */		
#define SYM895_SSTAT1_CD          0x04	 /* SCSI:CD Signal,Latched */		
#define SYM895_SSTAT1_IO          0x04   /* SCSI:IO Signal, Latched */		

/* SSTAT2 */

#define SYM895_SSTAT2_ILF1        0x80   /* SIDL MSB full */
#define SYM895_SSTAT2_ORF1        0x40   /* SODR MSB full */
#define SYM895_SSTAT2_OLF1        0x20   /* SODL MSB full */
#define SYM895_SSTAT2_FF4         0x10   /* FIFO flags bit 4 */
#define SYM895_SSTAT2_SPL1        0x08   /* Latched SCSI Parity for SIDL */
#define SYM895_SSTAT2_DM          0x04   /* DIFFSENS Mismatch */
#define SYM895_SSTAT2_LDSC        0x02   /* Last Disconnect;used in */
                                         /* conjunction with CON bit in SCNTL1*/
#define SYM895_SSTAT2_SDP1        0x01   /* SCSI SDP1/ parity signal */

/* ISTAT RW register */

#define SYM895_ISTAT_ABRT         0x80	 /* Abort operation */
#define SYM895_ISTAT_SOFTRST      0x40	 /* Soft chip reset */
#define SYM895_ISTAT_SIGP         0x20	 /* signal process */
#define SYM895_ISTAT_SEM          0x10   /* Semaphore */
#define SYM895_ISTAT_CON          0x08	 /* stat connected (reset doesn't */
                                         /* disconnect) */
#define SYM895_ISTAT_INTF         0x04   /* set by INTFLY script instruction.*/
                                         /* Signals ISRs while scripts are   */    
                                         /* still running */
#define SYM895_ISTAT_SIP          0x02   /* SCSI Interrupt Pending */
#define SYM895_ISTAT_DIP          0x01   /* Dma Interrupt Pending */

/* CTEST0 */

#define SYM895_CTEST1_FMT_MASK	  0xf0   /* Byte Empty in DMA Fifo */
#define SYM895_CTEST1_FFL_MASK	  0x0f   /* Byte Full in DMA Fifo */

/* CTEST2 */

#define SYM895_CTEST2_DDIR        0x80   /* Data Direction. 1 => From */
                                         /* SCSI to board */
#define SYM895_CTEST2_SIGP        0x40	 /* Signal Process. Same as in ISTAT.*/
                                         /* When this register is read SIGP  */
                                         /* is cleared in ISTAT */
#define SYM895_CTEST2_CIO         0x20   /* Configured as I/O  */
#define SYM895_CTEST2_CM          0x10	 /* Configured as Memory */
#define SYM895_CTEST2_SRTCH       0x08   /* Configure Scratch regs */
#define SYM895_CTEST2_TEOP        0x04   /* Scsi True end of process */
#define SYM895_CTEST2_DREQ        0x02   /* Data Request Status */
#define SYM895_CTEST2_DACK        0x01	 /* Data Acknowledge Status */

/* CTEST3 */

#define SYM895_CTEST3_REV_MASK    0xf0	 /* Chip Revision Mask */
#define SYM895_CTEST3_FLF         0x08	 /* Flush DMA FIFO */
#define SYM895_CTEST3_CLF         0x04	 /* Clear DMA FIFO */
#define SYM895_CTEST3_FM          0x02	 /* Fetch Pin Mode */
#define SYM895_CTEST3_WRIE        0x01	 /* Write and Invalidate Enable */

/* DFIFO */

#define SYM895_FIFO_112_MASK      0x7f   /* 7 bits of Byte Offset counter */
                                         /* between  SCSI core and DMA core */
#define SYM895_FIFO_816_MASK      0x3ff  /* 10 bits (8 - DFIFO, 2 - CTEST5 ) */
                                         /* of SCSI Byte Offset counter */
                                         /* between  SCSI core and DMA core */

/* CTEST4 */

#define SYM895_CTEST4_BDIS        0x80   /* Burst transfer DISable */
#define SYM895_CTEST4_ZMOD        0x40	 /* High Impedance Mode */
#define SYM895_CTEST4_ZSD         0x20	 /* SCSI data high impedance */
#define SYM895_CTEST4_SRTM        0x10	 /* Shadow Register Test Mode */
#define SYM895_CTEST4_MPEE        0x08   /* Master Parity Error Enable */
#define SYM895_CTEST4_FBL_MASK    0x07   /* Fifo byte control */

/* CTEST5 */

#define SYM895_CTEST5_ADCK        0x80   /* Increment DNAD register */
#define SYM895_CTEST5_BBCK        0x40   /* Decrement DBC register */
#define SYM895_CTEST5_DFS         0x20   /* DMA FIFO Size: 0=112, 1=816 bytes */
#define SYM895_CTEST5_MASR        0x10   /* Master Ctrl for Set/Reset Pulses */
#define SYM895_CTEST5_BL2         0x04   /* Burst Length bit 2 */
#define SYM895_CTEST5_BO9         0x02   /* b9 of DMA Fifo byte offset counter*/
#define SYM895_CTEST5_BO8         0x01   /* b8 of DMA Fifo byte offset counter*/

/* CTEST6 */

#define SYM895_CTEST6_DF_MASK     0xff   /* Dma Fifo bits - mask */

/* DMODE RW register */

#define SYM895_DMODE_BL1          0x80   /* Burst Length transfer bits; */
                                         /* determine the number of transfers */
                                         /* per bus ownership */
#define SYM895_DMODE_BL0          0x40	 /* 00=2,01=4,10=8,11=16 */
#define SYM895_DMODE_SIOM         0x20	 /* Source I/O Memory Enable; */
                                         /* 1 => I/O */
#define SYM895_DMODE_DIOM         0x10   /* Destination I/O Memory Enable; */
#define SYM895_DMODE_ERL          0x08   /* Enable PCI Read Line command */
#define SYM895_DMODE_ERMP         0x04   /* Enable PCI Read Multiple command */
#define SYM895_DMODE_BOF          0x02   /* Burst Opcode Fetch enable; */
                                         /* instrs fetched in burst mode */
#define SYM895_DMODE_MAN          0x01   /* Manual start mode ,when set   */
                                         /* disable autostart script when */ 
                                         /* writting in DSP */

/* DCNTL - DMA Control bits */

#define SYM895_DCNTL_CLSE         0x80   /* Cache Line Size Enable */
#define SYM895_DCNTL_PFF          0x40   /* Pre-Fetch Flush */
#define SYM895_DCNTL_PFEN         0x20   /* Pre-Fetch ENable */ 
#define SYM895_DCNTL_SSM          0x10   /* Single-Step Mode */
#define SYM895_DCNTL_IRQM         0x08   /* IRQ Mode */
#define SYM895_DCNTL_STD          0x04   /* Start Dma operation; */
#define SYM895_DCNTL_IRQD         0x02   /* IRQ Disable */
#define SYM895_DCNTL_COM          0x01   /* Compatability 1 => ncr700 mode  */

/* 
 * SIEN0 (enable intr)and SIST0 (RO Status) 
 * Enable interrupt 
 */

#define SYM895_B_MA            0x80  /* Phase Mismatch / ATN interrupt*/
#define SYM895_B_CMP           0x40  /* Funtion CoMPlete; interrupt when full */ 
                                     /* arbitration and selection is complete */
#define SYM895_B_SEL           0x20  /* Selected; intr when selected as tgt */
#define SYM895_B_RSL           0x10  /* Reselected; intr when reselected */
#define SYM895_B_SGE           0x08  /* SCSI Gross Error; intr enable */
#define SYM895_B_UDC           0x04  /* Enable Unexpected Disconnect intr */
#define SYM895_B_RST           0x02  /* Enable Reset intr */
#define SYM895_B_PAR           0x01  /* Enable parity intr */

/* SIEN1 (enable intr) and SIST1 (RO status) */

#define SYM895_B_SBMC          0x10  /* SCSI Bus Mode Change Interrupt */
#define SYM895_B_STO           0x04  /* Selection/Reselection Timeout */
#define SYM895_B_GEN           0x02  /* GENeral purpose timer expired */
#define SYM895_B_HTH           0x01  /* Handshake to Handshake timer expired */

/* MACNTL - Memory Access Control (RW) */

#define SYM895_MACNTL_TYP_MASK 0xf0  /* Identify the chip type */
#define SYM895_MACNTL_DWR      0x08  /* Data WRite is local memeory access */
#define SYM895_MACNTL_DRD      0x04  /* Data ReaD is local memory access */
#define SYM895_MACNTL_PSCPT    0x02  /* Pointer to SCRIPTs is local mem access*/
#define SYM895_MACNTL_SCPTS    0x01  /* SCRIPTS fetch is local mem access */

/* 
 * GPCNTL - General Purpose Pin Control (RW) 
 * This reg is used to determine if GPREG pins are inputs or outputs 
 */

#define SYM895_GPCNTL_ME       0x80  /* Master Enable;internal busmaster:GPIO1*/
#define SYM895_GPCNTL_FE       0x40  /* Fetch Enable; */ 
                                     /* internal op-code fetch GPIO0*/
#define SYM895_GPCNTL_GPIO4    0x10  /* GPIO4: set - input and reset - output */
#define SYM895_GPCNTL_GPIO3    0x08  /* GPIO3: set - input and reset - output */
#define SYM895_GPCNTL_GPIO2    0x04  /* GPIO2: set - input and reset - output */
#define SYM895_GPCNTL_GPIO1    0x02  /* GPIO1: set - input and reset - output */
#define SYM895_GPCNTL_GPIO0    0x01  /* GPIO0: set - input and reset - output */

/* STIME0  SCSI Timer Zero (RW) */

/* These bits select various timeout values.e.g 0000 => disable; 1111 => 1.6s */

#define SYM895_STIME0_HTH_MASK 0xf0  /* Handshake-To-Handshake period mask*/
#define SYM895_STIME0_SEL_MASK 0x0f  /* SELection timeout mask */

/* STIME1 SCSI Timer One (RW) */

#define SYM895_STIME1_HTHBA    0x40  /* HTH Timer Bus Activity Enable */
#define SYM895_STIME1_GENSF    0x20  /* General Purpose Timer Scale Factor */
#define SYM895_STIME1_HTHSF    0x10  /* HTH Timer Scale Factor */
#define SYM895_STIME1_GEN_MASK 0x0f  /* GENeral timer timeout mask */

/* STEST0 SCSI Test Zero (RO) */

#define SYM895_STEST0_SSAID_MASK    0xf0 /* SCSI Selected As ID */
#define SYM895_STEST0_SLT           0x08 /* Selection response logic test */
#define SYM895_STEST0_ART           0x04 /* Arbitation Priority encoder Test */
#define SYM895_STEST0_SOZ           0x02 /* SCSI Synchronous Offset Zero */
#define SYM895_STEST0_SOM           0x01 /* SCSI Synchronous Offset Maximum */

/* STEST1 SCSI Test One (RW) */

#define SYM895_STEST1_SCLK          0x80 /* Disables external SCLK and uses */
                                         /* PCI internal SCSI clock */
#define SYM895_STEST1_SISO          0x40 /* SCSI Isolation Mode; inputs  */
                                         /* isolated from the SCSI bus */
#define SYM895_STEST1_QEN           0x08 /* Enable: Power on clock Quadrupler */
#define SYM895_STEST1_QSEL          0x04 /* Select: Increase clock to 160 MHz */