rominit.s

LoPEC Early Access VxWorks BSP

	/* 
	 * Enable floating point support in the processor so that
	 * we can scrub memory using 64 bit reads and writes.
	 */
 
	lis	r3,HI(1<<(31-_PPC_MSR_BIT_FP))	    /* 0x00002000 */
	ori	r3,r3,LO(1<<(31-_PPC_MSR_BIT_FP))
	mtmsr	r3

	bl 	loadScrubData	

	.long 0x00000000,0x00000000

loadScrubData:

	mfspr	r4,LR			/* address of the above table of 0's */
	lfd 	0,0(r4)			/* load the 0's into fpr0 */
	
	
	/* Setup scrub loop specifics */

	subf	r18,r13,r14		/* calculate number of bytes */
	rlwinm	r18,r18,29,3,31		/* calculate number of doubles */
	addi	r17,r13,-8		/* starting address munged */
	mtspr	9,r18			/* load number of doubles/words */

	/* Loop through the entire DRAM array, initialize memory */

scrubLoop:

	stfdu	0,8(r17)		/* write contents of fpr0 to memory */
	bc	16,0,scrubLoop 		/* branch until counter == 0 */

	sync
	mtspr	9,r18			/* load number of doubles/words */
	addi	r17,r13,-8		/* starting address munged */

readLoop:

	/* 
	 * It is necessary to read the memory after writing it, to
	 * ensure that all data has been flushed from the cache and
	 * has been written to memory.
	 */
 
	lfdu	0,8(r17)		/* read memory into fpr0 */
	bc	16,0,readLoop		/* branch until counter == 0 */
	
scrubExit:
	mtspr	8,r16			/* restore return instruction pointer */
	bclr	0x14,0x0		/* return to caller */


/******************************************************************************
*
* mpc107RegMod - PCI configuration register modification.
*
* This function	provides modification control for mpc107's
* configuration	registers.  It performs	the necessary byte
* swapping.
*
* call:
*     mpc107RegMod(regOffset, regSize, mask, data)
*
*     regOffset	= (r3) address of device register to be	modified
*     regSize		= (r4) register	size
*	  1, byte (8 bit) register
*	  2, half word (16 bit/2 byte) register
*	  4, word (32 bit/4 byte) register
*     mask		= (r5) mask for	current	register value
*     data		= (r6) data to be inserted into	register
*     spr8		= return program counter
*
* registers used (and not saved):
*	r3, r4,	r5, r6,	r7, r8,	r9, r20
*
* RETURNS:
*    (r3) data read from register if read operation (otherwise return 0)
*/

	.text
	.align	2
	.globl	mpc107RegMod
mpc107RegMod:
	sync				/* ensure instructions are complete */
	eieio				/* ensures memory access is complete */
	xor	r0,r0,r0		/* clear r0 */

	/* load register addresses to device-register, PCI_CAR, and PCI_CDR */

	addis	r7,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r7,r7,LO(CNFG_PCI_HOST_BRDG)
	add	r7,r7,r3		/* add register offset */
	addis	r8,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r8,r8,LO(PCI_MSTR_PRIMARY_CAR)
	addis	r9,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r9,r9,LO(PCI_MSTR_PRIMARY_CDR)

	/* adjust the addresses to CDR and device-register */

	andi.	r12,r3,0x3		/* mask register offset */
	add	r9,r9,r12		/* adjust it */
	addi	r12,r0,0x3		/* load mask (lower 2-bits) */
	andc	r7,r7,r12		/* mask of lower 2-bits */

	/* write register value to CAR */

	stwbrx	r7,r0,r8		/* write register value to CAR */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */

	/* determine the size of the data operation */

	cmpli	0,0,r4,0x04		/* is this a word i/o operation? */
	bc	0x0c,0x02,andor32	/* branch to word i/o code */
	cmpli	0,0,r4,0x02		/* is this a half-word i/o operation? */
	bc	0x0c,0x02,andor16	/* branch to half-word i/o code */
	cmpli	0,0,r4,0x01		/* is this a byte i/o operation? */
	bc	0x0c,0x02,andor8	/* branch to byte i/o code */
	bclr	0x14,0x0		/* return to caller */

	/* word size data operations */

andor32:				/* READ/MODIFY(AND/OR)/WRITE */
	lwbrx	r7,r0,r9		/* load(read) device data into r7 */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	stwbrx	r7,r0,r9		/* store(write) r7 to device reg */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	bclr	0x14,0x0		/* return to caller */

	/* half-word size data operations */

andor16:				/* READ/MODIFY(AND/OR)/WRITE */
	lhbrx	r7,r0,r9		/* load(read) device data into r7 */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	sthbrx	r7,r0,r9		/* store(write) r7 to device reg */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	bclr	0x14,0x0		/* return to caller */

	/* byte data size operations */

andor8:					/* READ/MODIFY(AND/OR)/WRITE */
	lbz	r7,0(r9)		/* load(read) device data into r7 */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	stb	r7,0(r9)		/* store(write) r7 to device reg */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	bclr	0x14,0x0		/* return to caller */


/******************************************************************************
*
* mpc107DefInit	- configure memory controller with default memory settings.
*
* This function	initializes the	mpc107 memory controller
* to bank 0, 32Mg and assumes a	83.3MHz	clock.
*
* registers used (and not saved):
*	r3, r4,	r5, r6,	r7, r8,	r9, r20
*
* RETURNS:
*     none
*/

	.text
	.align	3
	.globl	mpc107DefInit
mpc107DefInit:
	addis	r0,r0,0			/* insure r0 is zero */
	ori	r0,r0,0			/* insure r0 is zero */
	or	r22,r0,r0		/* preset to no memory available */
	mfspr	r20,8			/* save return instruction pointer */

	bl	mpc107InitTableBasicPtr	/* branch around tables */
/*
 *	register data table (initialization values)
 *
 *	this table places the mpc107 into a known state, other tables
 *	exist for specific memory configurations
 */
mpc107InitTableBasic:
/*
 *		reg size  data	      mask
 *		=== ====  ====	      ====
 */

	.long MPC107_CFG_CACHE_LINE_SIZE,	1, 0x08,	0x08  
	.long MPC107_CFG_LATENCY_TIMER,		1, 0x80,	0x80

	.long MPC107_CFG_PCI_ARBITER_CNTL,	2, 0x0000,	0x0000

	.long MPC107_CFG_PWR_MGT_CFG_REG,	2, 0x0000,	0x0000
	.long MPC107_CFG_PWR_MGT_CFG_REG2,	1, 0xE0,	0x00
	.long MPC107_CFG_OUTPUT_DRIVER_REG,	1, 0xcf,	0x00

	.long MPC107_CFG_CLOCK_DRIVER_REG,	2, 0x0300,	0x0000
	.long MPC107_CFG_MISC_DRIVER_CNTL_REG,  1, 0x00,	0x00
	.long MPC107_CFG_EUMBBAR,		4, MPC107_EUMB_BASE, 0x00000000

	.long MPC107_CFG_MEM_STRT_ADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_MEM_STRT_UADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_STRT_ADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_ST_UADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_MEM_END_ADR_REG,	4, 0x001f0000,	0x00000000
	.long MPC107_CFG_MEM_END_UADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_END_ADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_END_UADR_REG,	4, 0x00000000,	0x00000000

	.long MPC107_CFG_MEM_BANK_ENABLE_REG,	1, 0x04,	0x00
	.long MPC107_CFG_PAGE_MODE_CTR_TIMER,	1, 0x00,	0x00

	.long MPC107_CFG_PROC_IF_CFG1,		4, 0xFF141010,	0x00000000
	.long MPC107_CFG_PROC_IF_CFG2,		4, 0x000C060C,	0x00000000

	.long MPC107_CFG_ECC_ERROR_CTR,		1, 0x00,	0x00
	.long MPC107_CFG_ECC_ERROR_TRIG,	1, 0x00,	0x00

	.long MPC107_CFG_ERROR_ENABLE1,		1, 0x00,	0x00
	.long MPC107_CFG_ERROR_DETECT1,		1, 0x00,	0x00
	.long MPC107_CFG_CPU_BUS_ERR_STAT,	1, 0x00,	0x00

	.long MPC107_CFG_ERROR_ENABLE2,		1, 0x00,	0x00
	.long MPC107_CFG_ERROR_DETECT2,		1, 0x00,	0x00
	.long MPC107_CFG_PCI_BUS_ERR_STAT,	1, 0x00,	0x00
	.long MPC107_CFG_CPU_PCI_ERR_ADR,	4, 0x0000e0fe,	0x00000000

	.long MPC107_CFG_MISC_REG1,		1, 0xc0,	0x00

	.long MPC107_CFG_MEM_CNTL_CFG_REG1,	4, 0x08ec0000,	0x00000000
	.long MPC107_CFG_MEM_CNTL_CFG_REG2,	4, 0x17601868,	0x00000000
	.long MPC107_CFG_MEM_CNTL_CFG_REG3,	4, 0x07400000,	0x00000000
	.long MPC107_CFG_MEM_CNTL_CFG_REG4,	4, 0x25103230,	0x00000000

	.long -1, -1, -1, -1			/* table end marker */

mpc107InitTableBasicPtr:
	mfspr	r21,8			/* load pointer to table */
mpc107InitBLoop:
	lwz	r3,0(r21)		/* load offset */
	lwz	r4,4(r21)		/* load size */
	lwz	r5,12(r21)		/* load mask (and-data) */
	lwz	r6,8(r21)		/* load data (or-data) */
	cmpi	0,0,r5,-1		/* table end? */
	bc	12,2,mpc107InitDone	/* if equal, yes, branch */
	bl	mpc107RegMod		/* perform register mod operation */
	addi	r21,r21,16		/* bump to next entry */
	b	mpc107InitBLoop		/* play it again sam */


mpc107InitDone:

/* exit routine, return to caller (probably start.s) */

	or	r3,r22,r22		/* return memory size in bytes */
	mtspr	8,r20			/* restore return instruction pointer */
	bclr	20,0			/* return to caller */

	.align	3


/******************************************************************************
*
* waitRefresh -	delays for at least 200	microseconds.
*
* This subroutine's purpose is delay execution for at least
* 200 micro seconds to allow a memory refresh to occur
* The routine assumes the fastest lopec clock (100MHz).
* 100MHz = 100,000,000 Hz or clock cycles/sec
* Decrementer counts down 1 value in 4 clock cycles.
* Want to wait 200 usecs or .0002 seconds.
*
*	  100,000,000 *	.0002 =	20,000 clock cycles.
*	  20,000/4 = 5000 clocks.
*
* registers used (and not saved):
*	r3
*
* RETURNS:
*     none
*/

	.text
	.align	3
	.globl	waitRefresh

waitRefresh:

	sync				/* ensure instructions are complete */
	eieio				/* ensures memory access is complete */

	addi	r3,r0,MEM_REFRESH_DELAY	/* 200 us on 100MHz bus */
	mtspr	22,r3			/* set decrementer to r3 */
	sync				/* ensure instructions are complete */

refreshLoop:
	mfspr	r3,22			/* load decrementer value */
	sync				/* ensure instructions are complete */

	cmpi	0,0,r3,0
	bc	12,1,refreshLoop	/* if r3 is > 0, branch */

	bclr	20,0			/* return to caller */

/******************************************************************************
*
* iCacheOn - Turn Instruction Cache On
*
* void iCacheOn	(void)
*/


	/* Enable Instruction Cache */

_iCacheOn:
iCacheOn:

	mfspr	r4,HID0			/* r4 = default */
	isync
	addi	r4,r0,0x1800		/* preprocessor work-around (0x8800) */
	addi	r4,r4,0x7000		/* r4 = ICE & ICFI bit */
	mtspr	HID0,r4			/* HID0 = Enable/Inval IC */
	isync
	addi	r3,r0,0x0800		/* r3 = ICFI bit */
	andc	r4,r4,r3		/* r4 = clear ICFI bit */
	mtspr	HID0,r4			/* HID0 = Enable IC */
	isync
	bclr	0x14,0x0

/******************************************************************************
*
* dCacheInval -	Invalidate Data	Cache
*
* void dCacheInval (void)
*/

_dCacheInval:
dCacheInval:
	addis	r3,r0,0x0000	       /* Setup bit pattern for DCFI + DCE */
	ori	r3,r3,(_PPC_HID0_DCE | _PPC_HID0_DCFI)
	mfspr	r4,HID0	       /* Modify HID0 to SET DCFI + DCE bits */
	or	r4,r4,r3
	sync		       /* required before changing DCE */
	mtspr	HID0,r4
	andc	r4,r4,r3       /* Modify HID0 to CLEAR DCFI + DCE bits */
	sync		       /* required before changing DCE */
	mtspr	HID0,r4
	bclr	0x14,0x0


/******************************************************************************
*
* dCacheOn - Turn Data Cache On
*
* void dCacheOn	(void)
*/

_dCacheOn:
dCacheOn:
	mfspr	r4,HID0	       /* Modify HID0 to enable D cache (DCE) */
	ori	r4,r4,_PPC_HID0_DCE
	sync		       /* required before changing DCE */
	mtspr	HID0,r4
	bclr	0x14,0x0

	.align	3

/******************************************************************************
*
* maxErrata - apply relevant errata workarounds for Max processor.
*
* RETURNS: N/A
*/

maxErrata:

	/* Get the MAX revision type. If 2.7 or less apply errata fix. */

	mfspr	r29,PVR
	rlwinm	r29,r29,0,24,31

	cmpwi	r29,7
	bc	12,5,cpuNotMax27	/* branch if greater than 7 */

	/*
	 * The following five instructions is a	workaround for errata #13
	 * as described	in "PowerPC Max	Microprocessor Errata List Release
	 * 2.x Chips", Errata Version 9	6/27/00.  Description: "Speculative
	 * instruction stream may cause	duplicate data cache tags".
	 */

	li	r2,0x0
	mtspr	1014,r2			/* MSSCR0 */

	lis	r2,HI(MEMSSCR1)
	ori	r2,r2,LO(MEMSSCR1)	/* MSSCR1: L1OPQ_SIZE=0x01000000 */
	mtspr	1015,r2

	/*
	 * The following five instructions is a	workaround for errata #7
	 * as described	in "PowerPC Max	Microprocessor Errata List Release
	 * 2.x Chips",Errata Version 9 6/27/00.	Description: "Store data
	 * lost	when store gathering is	enabled	during cache ops".
	 */

	mfspr	r2,HID0
	lis	r3,HI(SGE_CLEAR)	/* SGE: clear */
	ori	r3,r3,LO(SGE_CLEAR)
	andc	r2,r2,r3
	mtspr	HID0,r2

cpuNotMax27:

	bclr	20,0

/******************************************************************************
*
* nitroErrata - apply relevant errata workarounds for Nitro processor.
*
* RETURNS: N/A
*/

nitroErrata:

	/* Get the NITRO revision type. */

	mfspr	r29,PVR
	rlwinm	r29,r29,0,24,31

	cmpwi	r29,(CPU_REV_NITRO+2)
	bc	12,5,cpuNotNitro	/* branch if greater than 0x1102 */

	/*
	 * The following five instructions is a	workaround for errata #1
	 * as described	in "PowerPC Nitro Microprocessor Errata	List Release
	 * 1.x Chips",Errata Version 3 3/29/00.	Description: "Cache inhibited
	 * instruction fetches that hit	in L2 Direct Mapped SRAM space may
	 * cause processor hang".
	 */

	li	r2,0x0
	mtspr	1014,r2			/* MSSCR0 */

	lis	r2,HI(MEMSSCR1_NITRO)
	ori	r2,r2,LO(MEMSSCR1_NITRO)	/* MSSCR1: Nitro errata 1 */
	mtspr	1015,r2

	bclr	20,0