rominit.s

LoPEC Early Access VxWorks BSP

/* romInit.s - Motorola LoPEC ROM initialization module */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996,1997-2001 Motorola, Inc. All Rights Reserved */
	.data
	.globl	copyright_wind_river
	.long	copyright_wind_river

/*
modification history
--------------------
01j,23apr01,cak  changes to support registered DIMMs
01i,23mar01,cak  fixed broken ECC code, including scrub routine
01h,20feb01,scb  initialize cache line size and latency timer of mpc107
01g,12jan01,djs  modifications to support the use of SPD
01f,18dec00,scb  Tweak to get flash boot to work
01e,08dec00,djs  allow sysMemParamConfig to be called
01d,07dec00,scb  consolidated errata into callable functions, matching sysALIb.s
01c,28nov00,scb  put in BYPASS_SPD capability
01b,14nov00,scb  merged mv5100, prpmc800 items into mv2100 to support lopec
01a,02nov00,djs  created based on 01h,20Oct99,rhk mv2100
*/

/*
DESCRIPTION
This module contains the entry code for	the VxWorks bootrom.
The entry point	romInit, is the	first code executed on power-up.
It sets	the BOOT_COLD parameter	to be passed to	the generic
romStart() routine.

The routine sysToMonitor() jumps to the	location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows	a parameter to be passed to romStart().

This code is intended to be generic across PowerPC 603/604 boards.
Hardware that requires special register	setting	or memory
mapping	to be done immediately,	may do so here.
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "arch/ppc/mmu603Lib.h"

#define	CACHE_STACK_SIZE (8*1024)	/* stack size, 8KB */
#define	MEMSSCR1	0x01000000 /* Memory SubSystem Control Reg 1 */
#define	MEMSSCR1_NITRO	0x00040000 /* Nitro Memory SubSystem Control Reg 1 */
#define SGE_CLEAR 	0x00000080 /* SGE: clear */
#define DL1HWFLSH 	0x00800000 /* L1 data cache HW flush bit 8 */


/* ABI stack size must be >= sizeof(struct sramConfigReg) */

#define ABI_STACK_SIZE	 0x44	    

	/* Exported internal functions */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */

	/* externals */

	.extern	romStart	  /* system initialization routine */
	.extern	sysMemParamConfig /* memory parameter initialization */
	.extern	mpc107DefInit	  /* default memory initialization */
	.extern	waitRefresh

	.set	MCCR1,0
	.set	MCCR2,MCCR1+4
	.set	MCCR3,MCCR2+4
	.set	MCCR4,MCCR3+4

	.set	ERRENR1,MCCR4+4

	.set	MSR3_2_1_0,ERRENR1+4
	.set	MSR7_6_5_4,MSR3_2_1_0+4
	.set	MSER3_2_1_0,MSR7_6_5_4+4
	.set	MSER7_6_5_4,MSER3_2_1_0+4

	.set	MER3_2_1_0,MSER7_6_5_4+4
	.set	MER7_6_5_4,MER3_2_1_0+4
	.set	MEER3_2_1_0,MER7_6_5_4+4
	.set	MEER7_6_5_4,MEER3_2_1_0+4

	.set	MPMR,MEER7_6_5_4+4
	.set	MBER,MPMR+1

	.text
	.align 2

/******************************************************************************
*
* romInit - entry point	for VxWorks in ROM
*
* romInit
*     (
*     int startType	/@ only	used by	2nd entry point	@/
*     )
*/

_romInit:
romInit:
	/* 
	 * The following isync instruction is a workaround for errata #2
	 * as described in "PowerPC Max Microprocessor Errata List Release
	 * 2.x Chips", Errata Version 9 6/27/00.  Description: "Incorrect
	 * value was written to the MSR after running POR ABIST.
	 */

	isync				/* required for Max errata 2 */

	bl	cold

	bl	warm

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii	 "Copyright 1984-2000 Wind River Systems, Inc."
	.align 2

cold:
	li	r31,BOOT_COLD
	bl	start			/* skip over next instruction */

warm:
	or	r31,r3,r3		/* startType to r31 */

start:
	/*
	 * Socketed flash-ROM is at 0xfff00000
	 * Soldered flash-ROM is at 0xff000000
	 *
	 * Execution on powerup always begins at 0xfff00100.
	 *
	 * The determination as to whether or not to continue to
	 * execute out of socketed flash-ROM or to jump to soldered
	 * flash-ROM (0xff000100) is controlled by a bit in the
	 * configuration header register which represents the setting
	 * of dip switch zero.  If the dip switch is on, we want to
	 * jump to soldered flash (0xff000100), if it is off we want to
	 * continue to execute out of socketed flash-ROM (0xfff00100).
	 * It is up to the software to read the configuration header
	 * and conditionally branch to 0xff000100.
	 * 
	 * Note that PPC bug is also in one of the banks (normally but
	 * not necessarily the socketed bank) and it has to make the
	 * same determination.  Thus the following snippet of code (up
	 * to romExecution:) is present in both the PPC bug and the
	 * vxWorks "romInit.s" module.  The algorithm is:
	 *                        ...
	 * if execution address is currently > 0xff80ffff
	 *     {
	 *     if dip switch zero is "on" 
	 *         {
	 *         goto address ff000100 (Soldered ROM)
	 *         }
	 *     }
	 *
	 * (continue here dip switch 0 is off)
	 *
	 * romExecution:
	 *                        ...
	 */
          
	/* identify execution point as far as socketed or soldered. */

	bl	lreg			/* br below. load link reg w/ eaddr */
lreg:
	mfspr	r3,8			/* copy current instruction address */
	rlwinm	r3,r3,16,16,31		/* r3 = ((r3 >> 16) & 0x0000FFFF)   */
	cmpli	0,0,r3,0xFF80		/* If flash address (< 0xff800000), */
	bc	12,0,romExecution	/* proceed to flash image */

	/* check bit 0 of software configuration header */

	addis	r3,r0,HIADJ(LOPEC_CONFIG_HDR_REG) /* load S/W header reg */
	ori	r3,r3,LO(LOPEC_CONFIG_HDR_REG)

	xor	r4,r4,r4		/* clear r4 */
	lbz	r4,0(r3)		/* read S/W readable header register */
	sync				/* ensure memory access is complete */
	andi.	r4,r4,0x80		/* mask Socketed/Soldered bit */
	cmpli	0,0,r4,0x80		/* Is dip switch on or off */
	beq	romExecution		/* if 1 (off), socketed ROM execution */

	/* else switch is "on", branch to soldered flash */

	addis	r3,r0,HIADJ(FLASH_TEXT_ADRS)	/* Flash address */
	ori	r3,r3,LO(FLASH_TEXT_ADRS)
	mtspr	8,r3
	sync				/* ensure memory access is complete */
	bclr	0x14,0x0		/* branch via the link register */

romExecution:

	/* Zero-out registers: r0 & SPRGs */

	xor	r0,r0,r0

	mtspr	272,r0
	mtspr	273,r0
	mtspr	274,r0
	mtspr	275,r0

	/* initialize the stack pointer */

	lis	sp,HI(STACK_ADRS)
	ori	sp,sp,LO(STACK_ADRS)

	/*
	 *	Set HID0 to a known state
	 *	Enable machine check input pin (EMCP) for DRAM ECC detection
	 */

	lis	r3,HI(_PPC_HID0_EMCP) 		/* 0x80000000 */
	ori	r3,r3,LO(_PPC_HID0_EMCP)
	sync
	isync
	mtspr	HID0,r3

    	/*
    	 * Set MPU/MSR to a known state
    	 * Turn on FP
    	 */

    	lis	r3,HI(1<<(31-_PPC_MSR_BIT_FP))	   /* 0x00002000 */
    	ori	r3,r3,LO(1<<(31-_PPC_MSR_BIT_FP))

	sync
	mtmsr	r3
	isync

	/* Init the floating point control/status register */

	mtfsfi	7,0x0
	mtfsfi	6,0x0
	mtfsfi	5,0x0
	mtfsfi	4,0x0
	mtfsfi	3,0x0
	mtfsfi	2,0x0
	mtfsfi	1,0x0
	mtfsfi	0,0x0
	isync

	/* Initialize the floating point data regsiters to a known state */

	bl	ifpdr_value
	.long	0x3f800000	/* 1.0 */
ifpdr_value:
	mfspr	r3,8
	lfs	f0,0(r3)
	lfs	f1,0(r3)
	lfs	f2,0(r3)
	lfs	f3,0(r3)
	lfs	f4,0(r3)
	lfs	f5,0(r3)
	lfs	f6,0(r3)
	lfs	f7,0(r3)
	lfs	f8,0(r3)
	lfs	f9,0(r3)
	lfs	f10,0(r3)
	lfs	f11,0(r3)
	lfs	f12,0(r3)
	lfs	f13,0(r3)
	lfs	f14,0(r3)
	lfs	f15,0(r3)
	lfs	f16,0(r3)
	lfs	f17,0(r3)
	lfs	f18,0(r3)
	lfs	f19,0(r3)
	lfs	f20,0(r3)
	lfs	f21,0(r3)
	lfs	f22,0(r3)
	lfs	f23,0(r3)
	lfs	f24,0(r3)
	lfs	f25,0(r3)
	lfs	f26,0(r3)
	lfs	f27,0(r3)
	lfs	f28,0(r3)
	lfs	f29,0(r3)
	lfs	f30,0(r3)
	lfs	f31,0(r3)
	sync
	b	dontTurnOffFP

	/*
	 *	Set MPU/MSR to a known state
	 *	Turn off FP
	 */

	andi.	r3,r3,0
	isync
	mtmsr	r3
	isync

dontTurnOffFP:
	/* Init the Segment registers */

	andi.	r3,r3,0
	isync
	mtsr	0,r3
	isync
	mtsr	1,r3
	isync
	mtsr	2,r3
	isync
	mtsr	3,r3
	isync
	mtsr	4,r3
	isync
	mtsr	5,r3
	isync
	mtsr	6,r3
	isync
	mtsr	7,r3
	isync
	mtsr	8,r3
	isync
	mtsr	9,r3
	isync
	mtsr	10,r3
	isync
	mtsr	11,r3
	isync
	mtsr	12,r3
	isync
	mtsr	13,r3
	isync
	mtsr	14,r3
	isync
	mtsr	15,r3
	isync

	/* Get cpu type */

	mfspr	r28,PVR
	rlwinm	r28,r28,16,16,31

	cmpwi	r28,CPU_TYPE_MAX
	bne	cpuNotMax

	/* MAX L1 Data Cache HW Flush per Max Book 4,Rev. 2.0 */

	lis	r2,HI(DL1HWFLSH)
	ori	r2,r2,LO(DL1HWFLSH)
	mtspr	1014,r2 /* MSSCR0 */

	/*
	 * required sync to guarantee that all data from the dL1 has
	 * been written to the system address interface.
	 */

	 sync

	 bl	maxErrata

cpuNotMax:

	 cmpli	0,0,r28,CPU_TYPE_NITRO
	 bne	cpuNotNitro

	 bl	nitroErrata

cpuNotNitro:

#ifdef USER_I_CACHE_ENABLE

	/* Turn on instruction cache */

	bl	iCacheOn
#endif

	cmpli	0,0,r31,BOOT_COLD	/* check for warm boot */
	bc	4,2,skipMemGo		/* if warm boot, skip mem cntlr init */

	/* Clear MEMGO in MCCR1 so we can make memory controller adjustments. */

	addis	r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r6,r6,LO(CNFG_PCI_HOST_BRDG)
	addi	r3,r6,MPC107_CFG_MEM_CNTL_CFG_REG1 /* add MCCR1 offset */
	addis	r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
	stwbrx	r3,r0,r7		/* write address of MCCR1 to CAR */
	sync				/* ensure memory access is complete */

	addis	r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
	lwbrx	r5,r0,r4		/* read MCCR1 */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(MPC107_MCC1_MEMGO)
	ori	r3,r3,LO(MPC107_MCC1_MEMGO)
	andc	r5,r5,r3		/* and in complement of MEMGO */
	stwbrx	r5,r0,r4		/* write new value to MCCR1 */
	sync				/* ensure memory access is complete */

	/*
	 * Configure the memory	controller in a	default	setting	so that
	 * we can create a stack and read the SPD/VPD data.
	 */

	bl	mpc107DefInit		/* (mpc107DefInit) */

	/* disable the DBATs */

	xor	r0,r0,r0
	mtspr	DBAT0U,r0
	mtspr	DBAT1U,r0
	mtspr	DBAT2U,r0
	mtspr	DBAT3U,r0
	sync

       /*
        * We need to configure the memory controller before we can use
        * RAM.  We need RAM before we can configure the memory
        * controller since we must call a C routine (which uses a RAM
        * stack) to read the SPD and compute the memory controller
        * programming values.  This "chicken and egg" problem is
        * solved by configuring the processor in such a way that it
        * uses its L1 cache in copyback mode as data RAM.  Because we
        * only need to use a small amount of memory and we operate in
        * copyback mode, all data reads and writes are confined
        * strictly to the L1 cache and no actual RAM accesses are
        * attempted.  The required stack for the C function is
        * confined strictly to the L1 cache.  Upon return the computed
        * values are used to actually program the memory controller.
        * The configuring which allows us to use the L1 cache as a
        * memory repository is done by the time we reach the
        * instruction " stwu sp,-ABI_STACK_SIZE(sp)".  This is the
        * first instruction in "romInit.s" that actually writes to
        * data memory, prior to that all reads and writes are strictly
        * to the PPC register set.  The "bl sysMemParamConfig" is the
        * call to the C function which returns the memory size in r3
        * along with several parameters on the L1 stack.
        *
	* The steps we are about to perform are:
        *
	* 1. Program the data BATs for memory management.  We
	*    must have some type of memory management operating
	*    if we are going to use data cache in copyback mode.
	*    Use the first three DBATs to access the first 768MB
	*    of system memory and the last DBAT to access the memory
	*    controller registers.  This is necessary in order to 
	*    configure the controller.  But, in order to scrub a
	*    full 1GB of memory, which the LoPEC supports, we must 
	*    reprogram the last DBAT before calling the memoryScrub
	*    routine.  Therefore, the last DBAT is reprogrammed right
	*    before the call to memoryScrub later in romInit.
        *
	* 2. Conditionally turn on the instruction cache.
        *
	* 3. Invalidate the data cache and TLB entries.
        *
	* 4. Enable the data MMU.
        *
	* 5. Turn on the data cache.