sysscsi.c

LoPEC Early Access VxWorks BSP

/* sysScsi.c - SCSI-2 initialization for sysLib.c */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc., All Rights Reserved */

#include "copyright_wrs.h"

/*
modification history
--------------------
01b,06feb01,cak  Removed sysScsiInByte() and sysScsiOutByte
01a,16jan01,cak  Ported to LoPEC from mv5100 (01p) 
*/

/* 
Description

This file contains the sysScsiInit() and related routines necessary for
initializing the SCSI subsystem. 

It also contains BSP-specific SCSI I/O routines required by the ncr810 driver.

The constant PCI2DRAM_BASE_ADRS must be defined in the BSP.
*/

#ifdef	INCLUDE_SCSI

/* includes */

#ifdef	INCLUDE_SCSI2
#   include "drv/scsi/ncr810.h"
#   ifdef INCLUDE_SYM_895
#      include "drv/scsi/sym895.h"
#   endif /* INCLUDE_SYM_895 */
#else
#   error INCLUDE_SCSI2 must be defined for use with this driver.
#endif /* INCLUDE_SCSI2 */

/* The following MACRO definitions will be done in config.h after SYM895 is
 * componentiaed. Temporarily done here.
 */


#define UNKNOWN -1

#include "tapeFsLib.h"

/* typedefs */

#ifdef INCLUDE_SYM_895
/* sym895 controller info */

typedef struct sym895Info
    {
    UINT32 pciBus;      /* PCI Bus Number */
    UINT32 pciDevice;   /* PCI Device Number */
    UINT32 pciFunc;     /* PCI Function Number */
    UINT32 pciDevType;  /* PCI Device ID */

    UINT32 iobaseCsr;   /* base address 1 */
    UINT32 membaseCsr;  /* base address 0 */
    UINT32 rambaseCsr;  /* base address x */
    char   irq; 	/* interrupt request number */
    } SYM895_INFO;

LOCAL SYM895_INFO sym895InfoTable =
    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN};

/* external declarations */

extern int   sym895PciMemOffset;
extern int   sym895DelayCount;
extern ULONG sym895Instructions;
extern ULONG sym895Wait[];
#endif /* INCLUDE_SYM_895 */

extern int   ncr810PciMemOffset;
extern int   ncr810DelayCount;
extern ULONG NCR810_INSTRUCTIONS;
extern ULONG ncr810Wait[];
extern BOOL  scsiDebug;
extern void  eieioExecute();
extern void  vxEieio ();
extern UCHAR sysInByte (ULONG);
extern void  sysOutByte (ULONG,UCHAR);

#ifdef  INCLUDE_SECONDARY_SCSI
/* global declarations */

SCSI_CTRL * pSysScsiCtrl2;
#endif  /* INCLUDE_SECONDARY_SCSI */

/* function declarations */

LOCAL void swapScript (UINT32 * start, UINT32 * end);

#ifdef INCLUDE_SYM_895
/*******************************************************************************
*
* sysSym895PciInit - initialize PCI specific configuration
*
* This routine searches PCI bus for a SYM895 host adapter device. If found,
* the device configuration is either read or set depending on whether 
* PCI_CFG_FORCE is defined or not.
*
*/

STATUS sysSym895PciInit(void)
    {

    int    pciBusNo;       /* PCI bus number              */
    int    pciDevNo;       /* PCI device number           */
    int    pciFuncNo;      /* PCI function number         */
    int    index = 0;      /* desired instance of device  */
    UINT16 devType;
    UINT32 membaseCsr;     /* base address 0              */
    UINT32 iobaseCsr;      /* base address 1              */
    UINT32 rambaseCsr;
    char   irq;	           /* IRQ level */
    static BOOL firstTime = TRUE;
    SYM895_INFO * sym895Res;

    sym895Res = &sym895InfoTable;

    /* Set CPU <-> PCI address offset */

    sym895PciMemOffset = PCI2DRAM_BASE_ADRS;

    /* 
     * For the PPC family, the memory is Big-Endian. Since the PCI bus is 
     * little endian,the sym895 scripts need to be byte swapped in memory. 
     * However, they should only be swapped the first time that 
     * sysSym895PciInit() is invoked.  
     */

    if (firstTime)
	{
        swapScript ((UINT32 *) &sym895Wait, (UINT32 *) 
		    ((UINT32) &sym895Wait + 
		     (UINT32)(sym895Instructions * 8)));
        firstTime = FALSE;
	}

    /* Try to automatically configure SYM895 controller. */

    if ((pciFindDevice (PCI_ID_SYMBIOS, NCR895A_DEVICE_ID,
			index, &pciBusNo, &pciDevNo, &pciFuncNo)) != OK) 
        {
        logMsg(" SYM53C895 SCSI controller not found\n", 0, 0, 0, 0, 0, 0); 
        return ERROR;
        }

    pciConfigInWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEVICE_ID, &devType);

    /* read the configuration parameters */

    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0, 
                    &iobaseCsr);    
    pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEV_INT_LINE, 
                    &irq);
    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_1, 
                    &membaseCsr);
    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2, 
                    &rambaseCsr);

    iobaseCsr  &= PCI_IOBASE_MASK;
    iobaseCsr  += (ISA_MSTR_IO_LOCAL - ISA_MSTR_IO_BUS);

    /* update the device specific info */

    sym895Res->pciBus     = pciBusNo;
    sym895Res->pciDevice  = pciDevNo;
    sym895Res->pciFunc    = pciFuncNo;
    sym895Res->pciDevType = devType;
    sym895Res->irq        = irq;
    sym895Res->iobaseCsr  = iobaseCsr;
    sym895Res->membaseCsr = membaseCsr;
    sym895Res->rambaseCsr = rambaseCsr;


    return OK;

}
#endif /* INCLUDE_SYM_895 */


/*******************************************************************************
*
* sysScsiInit - initialize an on-board SCSI port
*
* This routine creates and initializes an NCR 53C8\f2xx\f1 SCSI I/O
* processor (SIOP) structure, enabling use of the on-board SCSI port.  It
* connects the proper interrupt service routine to the desired vector, and
* enables the interrupt at the desired level.
*
* RETURNS: OK, or ERROR if the SIOP structure cannot be created, the
* controller cannot be initialized, valid values cannot be set up in the
* SIOP registers, or the interrupt service routine cannot be connected.
*/
 
STATUS sysScsiInit ()
    {
#ifndef INCLUDE_SYM_895
    int                   pciBusNo;
    int                   pciDevNo;
    int                   pciFuncNo;
    UINT16                devType;
#endif /* INCLUDE_SYM_895 */
#ifdef  INCLUDE_SECONDARY_SCSI
    UINT16                devType2;
#endif	/* INCLUDE_SECONDARY_SCSI */
#ifndef INCLUDE_SYM_895
    static BOOL firstTime = TRUE;
    UINT32 iobaseCsr;               /* base address 0 */
    char irq;	                    /* IRQ level */	
 
    /* Local structure(s) with a prefill for ncr825SetHwRegister */

    static NCR810_HW_REGS hwRegs  = SYS_REG_SIOP_HW_REGS;
#endif /* INCLUDE_SYM_895 */
#ifdef  INCLUDE_SECONDARY_SCSI
    static NCR810_HW_REGS hwRegs2 = SYS_REG_SIOP_HW_REGS;
#endif  /* INCLUDE_SECONDARY_SCSI */

#ifdef INCLUDE_SYM_895

#   define  ULTRA2_SCSI_OPTIONS SYM895_ULTRA2_SCSI_OPTIONS
#   define  FAST_SCSI_OPTIONS   SYM895_FAST_SCSI_OPTIONS

#ifdef ULTRA2_SCSI
    static SYM895_HW_OPTIONS hwOptions = ULTRA2_SCSI_OPTIONS;
#else  /* ULTRA2_SCSI */
    static SYM895_HW_OPTIONS hwOptions = FAST_SCSI_OPTIONS;
#endif /* ULTRA2_SCSI */

    SYM895_INFO * sym895Resource;

    sym895Resource = &sym895InfoTable;
    
    sysSym895PciInit();

    /* Create the SCSI controller */

#ifdef ULTRA2_SCSI
    if ((pSysScsiCtrl = (SCSI_CTRL *) sym895CtrlCreate (
        (UINT8 *)sym895Resource->iobaseCsr, SYM895_160MHZ, 
        sym895Resource->pciDevType,
        (UINT8 *)sym895Resource->rambaseCsr, 0)) == NULL)
#else /* ULTRA2_SCSI */
    if ((pSysScsiCtrl = (SCSI_CTRL *) sym895CtrlCreate (
        (UINT8 *)sym895Resource->iobaseCsr, SYM895_40MHZ, 
        sym895Resource->pciDevType,
        (UINT8 *)sym895Resource->rambaseCsr, 0)) == NULL)
#endif /* ULTRA2_SCSI */
        {
        logMsg ("Could not create SCSI controller....\n",
                0, 0, 0, 0, 0, 0);
        return (ERROR);
        }

    if (intConnect (INUM_TO_IVEC ((int)sym895Resource->irq),
                        sym895Intr, (int) pSysScsiCtrl) == ERROR)
        {
	logMsg ("Could not connect interrupt....\n",
                0, 0, 0, 0, 0, 0); 
	return (ERROR);
        }

    intEnable(sym895Resource->irq) ;
	
    if (sym895CtrlInit ((SYM895_SCSI_CTRL *)pSysScsiCtrl, 
        SCSI_DEF_CTRL_BUS_ID) == ERROR)
        {
        logMsg (" Could not Initialize the Controller...\n",
                0, 0, 0, 0, 0, 0);
        return (ERROR);
        }

#if (USER_D_CACHE_MODE &  CACHE_SNOOP_ENABLE)

    scsiCacheSnoopEnable ((SCSI_CTRL *) pSysScsiCtrl);

#else 

    scsiCacheSnoopDisable ((SCSI_CTRL *) pSysScsiCtrl);

#endif
 
    if (sym895SetHwOptions ((SYM895_SCSI_CTRL *)pSysScsiCtrl, &hwOptions) != OK)
        {
        logMsg ("sym895SetHwOptions failed\n", 0, 0, 0, 0, 0, 0);
        return (ERROR);
        } 

#else /* INCLUDE_SYM_895 */

    /* Set CPU <-> PCI address offset */

    ncr810PciMemOffset = PCI2DRAM_BASE_ADRS;

    /* 
     * Since the PCI bus is little endian, and the PPC CPU's are big endian,
     * the ncr8xx scripts need to be byte swapped in memory. However, they
     * should only be swapped the first time that sysScsiInit() is invoked.
     */

    if (firstTime)
	{
        swapScript ((UINT32 *) &ncr810Wait, (UINT32 *) 
		    ((UINT32) &ncr810Wait + 
		     (UINT32)(NCR810_INSTRUCTIONS * 8)));
	firstTime = FALSE;
	}

    /* Try to automatically configure the correct type of NCR8XX controller. */

    if (pciFindDevice ((PCI_ID_SCSI & 0xFFFF), ((PCI_ID_SCSI >> 16) & 0xFFFF),
                       0, &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)
        {
	/* Get Device ID */

	pciConfigInWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEVICE_ID, &devType);

	SCSI_DEBUG_MSG ("Found Primary SCSI Controller - Dev/Ven ID = 0x%x\n", PCI_ID_SCSI,0,0,0,0,0);
	}
    else 
	{
	logMsg ("SCSI controller not found\n", 0, 0, 0, 0, 0, 0);
        return (ERROR);
	}

    devType = NCR875_DEVICE_ID; /* Force ncr810Lib to think this is a 875 */

#ifndef SCSI_WIDE_ENABLE
    devType = NCR810_DEVICE_ID;
#endif

    ncr810DelayCount = NCR810_DELAY_MULT;

    /* read the configuration parameters */

    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0, 
                    &iobaseCsr);    
    pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEV_INT_LINE, 
                    &irq);

    iobaseCsr  &= PCI_IOBASE_MASK;
    iobaseCsr  += (ISA_MSTR_IO_LOCAL - ISA_MSTR_IO_BUS);

    /* Create the SCSI controller */

    if ((pSysScsiCtrl = (SCSI_CTRL *) ncr810CtrlCreate 
					  (
					  (UINT8 *) iobaseCsr,
					  (UINT)    NCR810_40MHZ,
					            devType      
					  )) == NULL)
        {
        return (ERROR);
        }
 
    /* connect the SCSI controller's interrupt service routine */
 
    if (intConnect (INUM_TO_IVEC ((int)irq),
                    ncr810Intr, (int) pSysScsiCtrl) == ERROR)
        {
        return (ERROR);
        }
 
    /* Enable SCSI interrupts */

    intEnable (irq);

    /* initialise SCSI controller with default parameters (user tuneable) */
 
    if (ncr810CtrlInit ((NCR_810_SCSI_CTRL *)pSysScsiCtrl, 
			SCSI_DEF_CTRL_BUS_ID) == ERROR)
        return (ERROR);

#if (USER_D_CACHE_MODE &  CACHE_SNOOP_ENABLE)

    scsiCacheSnoopEnable ((SCSI_CTRL *) pSysScsiCtrl);

#else 

    scsiCacheSnoopDisable ((SCSI_CTRL *) pSysScsiCtrl);

#endif

    /*
     * Set the good value in the registers of the SIOP coupled
     * with the hardware implementation
     */

    if (ncr810SetHwRegister ((NCR_810_SCSI_CTRL *)pSysScsiCtrl, &hwRegs) 
	== ERROR)
        return(ERROR);

#endif /* INCLUDE_SYM_895 */

#ifdef  INCLUDE_SECONDARY_SCSI
 
    if (pciFindDevice ((PCI_ID_SEC_SCSI & 0xFFFF),
			    ((PCI_ID_SEC_SCSI >> 16) & 0xFFFF), 0, &pciBusNo,
			    &pciDevNo, &pciFuncNo) != ERROR)
        {
	/* Get Device ID */

	pciConfigInWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEVICE_ID, &devType2);

	SCSI_DEBUG_MSG ("Found Secondary SCSI Controller - Dev/Ven ID = 0x%x\n", PCI_ID_SCSI,0,0,0,0,0);
	}
    else 
	{
	logMsg ("Secondary SCSI controller not found\n", 0, 0, 0, 0, 0, 0);
        return (ERROR);
	}

#ifndef SCSI_WIDE_ENABLE
    devType2 = NCR810_DEVICE_ID;
#endif

    ncr810DelayCount = (sysGetBusSpd () * NCR810_DELAY_MULT);

    /* read the configuration parameters */

    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0,