mpc107.h

LoPEC Early Access VxWorks BSP

#define MPC107_CFG_DEV_INT_PIN		0x3d	/* interrupt pin */
#define MPC107_CFG_MIN_GRANT		0x3e	/* minimum grant */
#define MPC107_CFG_MAX_LATENCY		0x3f	/* maximum latency */
#define MPC107_CFG_PCI_ARBITER_CNTL	0x46	/* PCI arbiter control */
#define MPC107_CFG_PERF_MON_CMND_REG	0x48	/* performance mon command */
#define MPC107_CFG_PERF_MON_CNTL_REG	0x4c	/* perf monitor mode ctl */
#define MPC107_CFG_PERF_MON_COUNTER0	0x50	/* perf monitor counter 0 */
#define MPC107_CFG_PERF_MON_COUNTER1    0x54	/* perf monitor counter 1 */
#define MPC107_CFG_PERF_MON_COUNTER2    0x58	/* perf monitor counter 2 */
#define MPC107_CFG_PERF_MON_COUNTER3    0x5c	/* perf monitor counter 3 */
#define MPC107_CFG_PWR_MGT_CFG_REG	0x70	/* power mgmnt config */
#define MPC107_CFG_PWR_MGT_CFG_REG2	0x72	/* power mgmnt config 2 */
#define MPC107_CFG_OUTPUT_DRIVER_REG	0x73	/* output driver control */
#define MPC107_CFG_CLOCK_DRIVER_REG	0x74	/* clock driver control */
#define MPC107_CFG_MISC_DRIVER_CNTL_REG	0x76	/* misc driver control */
#define MPC107_CFG_EUMBBAR		0x78	/* Embedded Utils base addr */
#define MPC107_CFG_MEM_STRT_ADR_REG	0x80	/* memory starting address */
#define MPC107_CFG_MEM_STRT_UADR_REG	0x84	/* memory starting address up */
#define MPC107_CFG_EXT_MEM_STRT_ADR_REG 0x88	/* ext. mem start addr */
#define MPC107_CFG_EXT_MEM_ST_UADR_REG  0x8c	/* ext. mem start addr upper*/
#define MPC107_CFG_MEM_END_ADR_REG	0x90	/* memory end address */
#define MPC107_CFG_MEM_END_UADR_REG	0x94	/* memory end address upper */
#define MPC107_CFG_EXT_MEM_END_ADR_REG  0x98	/* ext. mem ending addr */
#define MPC107_CFG_EXT_MEM_END_UADR_REG 0x9c	/* ext. mem ending addr upper */
#define MPC107_CFG_MEM_BANK_ENABLE_REG  0xa0	/* memory bank enable */
#define MPC107_CFG_PAGE_MODE_CTR_TIMER  0xa3	/* page mode counter/timer */
#define MPC107_CFG_PROC_IF_CFG1		0xa8	/* processor interface config */
#define MPC107_CFG_PROC_IF_CFG2		0xac	/* processor interf config 2 */
#define MPC107_CFG_ECC_ERROR_CTR	0xb8	/* ECC single bit err counter */
#define MPC107_CFG_ECC_ERROR_TRIG	0xb9	/* ECC single bit err trigger */
#define MPC107_CFG_ERROR_ENABLE1	0xc0	/* error enable 1 */
#define MPC107_CFG_ERROR_DETECT1	0xc1	/* error detect 1 */
#define MPC107_CFG_CPU_BUS_ERR_STAT	0xc3	/* CPU bus error status */
#define MPC107_CFG_ERROR_ENABLE2	0xc4	/* error enable 2 */
#define MPC107_CFG_ERROR_DETECT2	0xc5	/* error detect 2 */
#define MPC107_CFG_PCI_BUS_ERR_STAT	0xc7	/* PCI bus error status */
#define MPC107_CFG_CPU_PCI_ERR_ADR	0xc8	/* CPU/PCI bus error address */
#define MPC107_CFG_MISC_REG1		0xe0	/* emulation support config */
#define MPC107_CFG_MEM_CNTL_CFG_REG1	0xf0	/* memory control config 1 */
#define MPC107_CFG_MEM_CNTL_CFG_REG2	0xf4	/* memory control config 2 */
#define MPC107_CFG_MEM_CNTL_CFG_REG3    0xf8	/* memory control config 3 */
#define MPC107_CFG_MEM_CNTL_CFG_REG4    0xfc	/* memory control config 4 */

/* MPC107 Configuration registers accessible from the PCI bus */

#define MPC107_CFG_LMBAR		0x10	/* local mem base addr reg */
#define MPC107_CFG_PCSRBAR		0x14	/* periph ctrl/stat base adr */

/* MPC107 Configuration Register Bit Definitions */

/* Offset 0x04 - MPC107 Command Register Bits */

#define MPC107_CMD_IO_ENABLE       0x0001  /* IO access enable */
#define MPC107_CMD_MEM_ENABLE      0x0002  /* memory access enable */
#define MPC107_CMD_MASTER_ENABLE   0x0004  /* bus master enable */
#define MPC107_CMD_MON_ENABLE      0x0008  /* monitor special cycles enable */
#define MPC107_CMD_WI_ENABLE       0x0010  /* write and invalidate enable */
#define MPC107_CMD_SNOOP_ENABLE    0x0020  /* palette snoop enable */
#define MPC107_CMD_PERR_ENABLE     0x0040  /* parity error enable */
#define MPC107_CMD_WC_ENABLE       0x0080  /* wait cycle enable */
#define MPC107_CMD_SERR_ENABLE     0x0100  /* system error enable */
#define MPC107_CMD_FBTB_ENABLE     0x0200  /* fast back to back enable */

/* Offset 0x06 - MPC107 PCI Status Register Bits */

#define MPC107_PCI_PARITY_ERR	   0x8000  /* PCI data or addr parity error */
#define MPC107_PCI_SYS_ERR	   0x4000  /* MPC107 asserts SERR */
#define MPC107_PCI_RCV_MSTR_ABORT  0x2000  /* MPC107 issued PCI master abort */
#define MPC107_PCI_RCV_TGT_ABORT   0x1000  /* received a PCI target abort */
#define MPC107_PCI_SIG_TGT_ABORT   0x0800  /* MPC107 issued PCI target abort */
#define MPC107_PCI_DATA_PARITY	   0x0100  /* data parity error detected */

/* Offset 0x0D - Latency Timer register */

#define MPC107_LAT_MAX_HOLD	0xf8	     /* max PCI clocks for bus hold */
#define MPC107_LAT_MIN_LAT	0x07	     /* min latency timer value */

/* Offset 0x46 - PCI arbiter control Register */

#define MPC107_PAC_IAE		0x00008000   /* internal arbiter enabled */
#define MPC107_PAC_PARK_MASK    0x00006000   /* park mode control mask */
#define MPC107_PAC_PARK_LAST    0x00000000   /* park mode cntrl, last device */
#define MPC107_PAC_PARK_REQ0    0x00002000   /* park mode using REQ0/GNT0) */
#define MPC107_PAC_PARK_MPC107  0x00004000   /* park mode control (MPC107) */
#define MPC107_PAC_RPCC         0x00000400   /* retry PCI configuration cycle */
#define MPC107_PAC_PPRI_LVL     0x00000080   /* MPC107 priority level: 1=high */
#define MPC107_PAC_EDPL_MASK    0x0000000f   /* ext dev priority lvl mask */
#define MPC107_PAC_EDPL_REQ0    0x00000008   /* ext dev pty lvl REQ3/GNT3 */
#define MPC107_PAC_EDPL_REQ1    0x00000004   /* ext dev pty lvl REQ2/GNT2 */
#define MPC107_PAC_EDPL_REQ2    0x00000002   /* ext dev pty lvl REQ1/GNT1 */
#define MPC107_PAC_EDPL_REQ3    0x00000001   /* ext dev pty lvl REQ0/GNT0 */

/* Offset 0x70 - power management configuration #1 Register */

#define MPC107_PMC1_NO_NAP_MSG      0x00008000 /* no message before nap */
#define MPC107_PMC1_NO_SLEEP_MSG    0x00004000 /* no message before sleep */
#define MPC107_PMC1_LP_REF_EN       0x00001000 /* rfrsh enbl in low pwr mode */
#define MPC107_PMC1_SUSP_QACK       0x00000400 /* QACK_ enable */
#define MPC107_PMC1_PM              0x00000080 /* power mananagement enable */
#define MPC107_PMC1_DOZE            0x00000020 /* doze mode */
#define MPC107_PMC1_NAP             0x00000010 /* nap mode */
#define MPC107_PMC1_SLEEP           0x00000008 /* sleep mode */
#define MPC107_PMC1_CKO_MODE_MASK   0x00000006 /* clock output mode - mask */
#define MPC107_PMC1_CKO_MODE_D      0x00000000 /* clk output mode - disable */
#define MPC107_PMC1_CKO_MODE_S      0x00000002 /* clk out mode - system clk */
#define MPC107_PMC1_CKO_MODE_1H     0x00000004 /* clk out mode - 1/2 PCI rate */
#define MPC107_PMC1_CKO_MODE_P      0x00000006 /* clk out mode - PCI rate */
#define MPC107_PMC1_CKO_SEL         0x00000001 /* clk out mode select */

/* Offset 0x72 - power management configuration #2 Register */

#define MPC107_PMC2_DLL_EXTEND      0x00000080 /* extend DLL by a half clock */
#define MPC107_PMC2_PCI_OHD_MASK    0x00000070 /* PCI out hold delay (mask) */
#define MPC107_PMC2_PCI_OHD_SHIFT   4
#define MPC107_PMC2_SLEEP           0x00000004 /* get PLL when exiting sleep */
#define MPC107_PMC2_SUSPEND         0x00000002 /* get PLL when exiting suspend*/
#define MPC107_PMC2_SHARED_MCP      0x00000001 /* disable MCP assertion */

/* Offset 0x73 - output driver control Register */

#define MPC107_ODC_DRV_PCI           0x00000080 /* PCI drive: 0=hi, 1=med */
#define MPC107_ODC_DRV_STD           0x00000040 /* STD drive: 0=hi, 1=med */
#define MPC107_ODC_DRV_MEM_CTRL_MASK 0x00000030 /* mem ctrl drive: mask */
#define MPC107_ODC_DRV_MEM_CTRL_40   0x00000000 /* mem ctrl drive: 40-ohms */
#define MPC107_ODC_DRV_MEM_CTRL_20   0x00000010 /* mem ctrl drive: 20-ohms */
#define MPC107_ODC_DRV_MEM_CTRL_13_3 0x00000020 /* mem ctrl drive: 13.3-ohms */
#define MPC107_ODC_DRV_MEM_CTRL_8    0x00000030 /* mem ctrl drive: 8-ohms */
#define MPC107_ODC_DRV_PCI_CLK_MASK  0x0000000c /* PCI clock drive: mask */
#define MPC107_ODC_DRV_PCI_CLK_40    0x00000000 /* PCI clock drive: 40-ohms */
#define MPC107_ODC_DRV_PCI_CLK_20    0x00000004 /* PCI clock drive: 20-ohms */
#define MPC107_ODC_DRV_PCI_CLK_13_3  0x00000008 /* PCI clock drive: 13.3-ohms */
#define MPC107_ODC_DRV_PCI_CLK_8     0x0000000c /* PCI clock drive: 8-ohms */
#define MPC107_ODC_DRV_MEM_CLK_MASK  0x00000003 /* mem clock drive: mask */
#define MPC107_ODC_DRV_MEM_CLK_40    0x00000000 /* mem clock drive: 40-ohms */
#define MPC107_ODC_DRV_MEM_CLK_20    0x00000001 /* mem clock drive: 20-ohms */
#define MPC107_ODC_DRV_MEM_CLK_13_3  0x00000002 /* mem clock drive: 13.3-ohms */
#define MPC107_ODC_DRV_MEM_CLK_8     0x00000003 /* mem clock drive: 8-ohms */

/* Offset 0x74 - clock driver control Register */

#define MPC107_CDC_PCI_CLK_0        0x00004000  /* PCI_CLK(0) disable */
#define MPC107_CDC_PCI_CLK_1        0x00002000  /* PCI_CLK(1) disable */
#define MPC107_CDC_PCI_CLK_2        0x00001000  /* PCI_CLK(2) disable */
#define MPC107_CDC_PCI_CLK_3        0x00000800  /* PCI_CLK(3) disable */
#define MPC107_CDC_PCI_CLK_4        0x00000400  /* PCI_CLK(4) disable */
#define MPC107_CDC_SDRAM_CLK_0      0x00000040  /* SDRAM_CLK(0) disable */
#define MPC107_CDC_SDRAM_CLK_1      0x00000020  /* SDRAM_CLK(1) disable */
#define MPC107_CDC_SDRAM_CLK_2      0x00000010  /* SDRAM_CLK(2) disable */
#define MPC107_CDC_SDRAM_CLK_3      0x00000008  /* SDRAM_CLK(3) disable */

/* Offset 0xA8 - processor interface configuration #1 Register */

#define MPC107_PIC1_CF_BREAD_WS_MASK  0x00c00000  /* wait states mask */
#define MPC107_PIC1_CF_BREAD_WS_SHIFT 22
#define MPC107_PIC1_RCS0              0x00100000  /* ROM location */
#define MPC107_PIC1_PROC_TYPE_MASK    0x00060000  /* processor type mask */
#define MPC107_PIC1_PROC_TYPE_SHIFT   17
#define MPC107_PIC1_ADDRESS_MAP       0x00010000  /* address map */
#define MPC107_PIC1_FLASH_WR_EN       0x00001000  /* FLASH write enable */
#define MPC107_PIC1_MCP_EN            0x00000800  /* machine check enable */
#define MPC107_PIC1_CF_DPARK          0x00000200  /* processor data bus park */
#define MPC107_PIC1_STORE_GATHER      0x00000040  /* store gathering enable */
#define MPC107_PIC1_ENDIAN_MODE       0x00000020  /* endian mode */
#define MPC107_PIC1_CF_LOOP_SNOOP     0x00000010  /* PCI-to-mem snoop loop en */
#define MPC107_PIC1_CF_APARK          0x00000008  /* processor addr bus park */
#define MPC107_PIC1_SPECULATIVE       0x00000004  /* speculative PCI from */
						  /* memory read enable */

/* Offset 0xAC - processor interface configuration #2 Register */

#define MPC107_PIC2_NO_SER_ON_CFG   0x20000000  /* disable PCI serialization */
#define MPC107_PIC2_NO_SNOOP_EN     0x08000000  /* disable PCI snoop */
#define MPC107_PIC2_CF_FF0_LOCAL    0x04000000  /* ROM PCI address map */
#define MPC107_PIC2_FLSH_WR_LCK_EN  0x02000000  /* disable FLASH writes */
#define MPC107_PIC2_CF_SNOOP_WS_M   0x00c00000  /* snoop addr phase wait state*/
#define MPC107_PIC2_CF_SNOOP_WS_S   18          /* snoop addr wait shift */
#define MPC107_PIC2_CF_APHASE_WS_M  0x0000000c  /* proc addr phase wait states*/
#define MPC107_PIC2_CF_APHASE_WS_S  2           /* proc addr phase wait shift */

/* Offset 0xE0 - emulation support */

#define MPC107_ES_CPU_FD_ALIAS_EN   0x00000080  /* forward FDxxxxxx to PCI */
#define MPC107_ES_PCI_FD_ALIAS_EN   0x00000040  /* forward FDxxxxxx to CPU */
#define MPC107_ES_DLL_RESET	    0x00000020  /* reset the DLL */
#define MPC107_ES_PCI_COMPAT_HOLE   0x00000008  /* PCI compatibil hole enable */
#define MPC107_ES_PROC_COMPAT_HOLE  0x00000004  /* proc compatibility hole en */

/* Offset 0xC0 - error enable #1 Register */

#define MPC107_EE1_PCI_TARG_ABORT   0x00000080  /* PCI target abort */
#define MPC107_EE1_PCI_PERR_SLAVE   0x00000040  /* PCI slace PERR */
#define MPC107_EE1_MEM_SELECT       0x00000020  /* memory select */
#define MPC107_EE1_MEM_REFRESH      0x00000010  /* memory refresh overflow */
#define MPC107_EE1_PCI_PERR_MSTR    0x00000008  /* PCI master PERR */
#define MPC107_EE1_MEM_READ_PARITY  0x00000004  /* memory read parity */
#define MPC107_EE1_PCI_MSTR_ABORT   0x00000002  /* PCI master abort */
#define MPC107_EE1_LOCAL_BUS_ERROR  0x00000001  /* local bus error */

/* Offset 0xC1 - error detection #1 Register */

#define MPC107_ED1_SERR             0x00000080  /* SERR_ received */
#define MPC107_ED1_PCI_PERR_SLAVE   0x00000040  /* PCI slace PERR */
#define MPC107_ED1_MEM_SELECT       0x00000020  /* memory select */
#define MPC107_ED1_MEM_REFRESH      0x00000010  /* memory refresh overflow */
#define MPC107_ED1_CYCLE_SPACE      0x00000008  /* cycle type: 0=local, 1=PCI */
#define MPC107_ED1_MEM_READ_PARITY  0x00000004  /* memory read parity */
#define MPC107_ED1_ULBC_MASK        0x00000003  /* unsupported local bus */
						/* cycle mask */
#define MPC107_ED1_ULBC_NO_ERROR    0x00000000  /* no error detected */
#define MPC107_ED1_ULBC_UTA         0x00000001  /* unsupported transfer */
						/* attributes */

/* Offset 0xC3 - CPU Bus Error Status Register */

#define MPC107_CPU_BUS_ERR_TT_MASK    0x000000f8
#define MPC107_CPU_BUS_ERR_TSIZ_MASK  0x00000007

/* Offset 0xC4 - error enable #2 */

#define MPC107_EE2_PCI_ADRS_PARITY  0x00000080  /* PCI address parity error */
#define MPC107_EE2_ECC_MULTIBIT     0x00000008  /* ECC multi-bit error */
#define MPC107_EE2_60X_MEM_WRITE_P  0x00000004  /* 60X mem write parity error */
#define MPC107_EE2_FLASH_ROM_WRITE  0x00000001  /* Flash ROM write error */

/* Offset 0xC5 - error detection #2 Register */

#define MPC107_ED2_IEA              0x00000080  /* invalid error address */
#define MPC107_ED2_ECC_MULTIBIT     0x00000008  /* ECC multi-bit error */
#define MPC107_ED2_60X_MEM_WRITE_P  0x00000004  /* 60X mem write parity error */
#define MPC107_ED2_FLASH_ROM_WRITE  0x00000001  /* Flash ROM write error */

/* Offset 0xC7 - PCI Bus Error Status Register */

#define MPC107_CPU_BUS_TARGET	     0x00000010	/* 1=bus target, 0=bus master */
#define MPC107_CPU_BUS_ERR_C_BE_MASK 0x0000000f /* Bus Error Status mask */

/* Offset 0xF0 - memory control configuration #1 */

#define MPC107_MCC1_ROMNAL_MASK     0xf0000000  /* ROM nibble access time mask*/
#define MPC107_MCC1_ROMNAL_SHIFT    28
#define MPC107_MCC1_ROMFAL_MASK     0x0f800000  /* ROM first access time mask */
#define MPC107_MCC1_ROMFAL_SHIFT    23
#define MPC107_MCC1_DBUS_SIZE_MASK  0x00600000  /* ROM/FLASH DBUS size mask */
#define MPC107_MCC1_64N32           0x00400000  /* 64-bit external data path */
#define MPC107_MCC1_8N64            0x00200000  /* 8-bit ROM/Flash */
#define MPC107_MCC1_BURST           0x00100000  /* burst mode ROM */
#define MPC107_MCC1_MEMGO           0x00080000  /* enable RAM interface logic */
#define MPC107_MCC1_SREN            0x00040000  /* enable self refresh */
#define MPC107_MCC1_SREN_MASK       1           /* MCC1 Reg Self Refresh mask */
#define MPC107_MCC1_SREN_SHIFT      18
#define MPC107_MCC1_RAM_TYPE        0x00020000  /* RAM type: 0=SDRAM,1=FPM/EDO*/
#define MPC107_MCC1_PCKEN           0x00010000  /* enable parity checking */
#define MPC107_MCC1_ROW_ADRS_MASK   0x0000ffff  /* row address mask */

/* Offset 0xF4 - memory control configuration #2 Register */

#define MPC107_MCC2_TS_WAIT_TIMER_M 0xe0000000  /* ROM out disable timing  */
#define MPC107_MCC2_TS_WAIT_TIMER_S 29
#define MPC107_MCC2_ASRISE_MASK     0x1e000000  /* AS_ falling edge timing */
#define MPC107_MCC2_ASRISE_SHIFT    25
#define MPC107_MCC2_ASFALL_MASK     0x01e00000  /* AS_ rising edge timing */
#define MPC107_MCC2_ASFALL_SHIFT    21
#define MPC107_MCC2_PARITY_OR_ECC   0x00100000  /* ECC/parity mechanism */
#define MPC107_MCC2_WR_PAR_CHK_EN   0x00080000  /* write parity check enable */
#define MPC107_MCC2_RD_PARECC_EN    0x00040000  /* inline mem bus read parity */