mpc107.h

LoPEC Early Access VxWorks BSP

/* mpc107.h - MPC107 chip header file */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01h,23apr01,cak  changes to support registered DIMMs
01g,13jan01,djs  Changes for using SPD values to setup the memory controller
01f,13dec00,djs  Cleanup/rename macros
01e,28nov00,scb  Added extra #defines in support of BYPASS_SPD option
01d,20nov00,scb  Non-romInit.s processor support
01c,17nov00,djs  removed EXT interrupt source vectors
01b,14nov00,scb  Changes for "romInit.s" processor support
01a,02nov00,djs  created from 01f,08feb00,rhk mv2100/kahlua.h
*/

/*
This file contains Base address defines, register offsets and bit
definitions for the the MPC107 chip
*/

#ifndef INCmpc107h
#define INCmpc107h

#ifdef __cplusplus
extern "C" {
#endif

#ifdef  _ASMLANGUAGE
#define CAST(x)
#else
typedef volatile UINT32 VUINT32;        /* volatile unsigned word */
typedef volatile UINT16 VUINT16;        /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;          /* volatile unsigned byte */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

/*
 *	IBC Extensions to Standard PCI Config Header register offsets
 */
#define PCI_CFG_IBC_INTR_ROUTE	0x44
#define PCI_CFG_IBC_ARB_CTL	0x83

/* PCI Arbiter Control Register bit definitions */

#define ARB_CTL_GAT		(1 << 7)
#define ARB_CTL_TIMEOUT_TIMER	(1 << 2)
#define ARB_CTL_BUS_LOCK	(1 << 0)

/* Aux Clock Legacy */
#define DESTINATION_CPU0	0x00000001

/* MPC107 Base addresses */

#define MPC107_EUMB_SIZE	0x00100000
#define MPC107_EUMB_BASE	MPC107_REGISTERS_BASE

/* 
 * Base addresses for the compnents of the Embedded Utilities Memory
 * Block.  These form the base addresses for the bulk of the MPC107
 * registers and are offset from the MPC107_EMBEDDED_UTILS_MEM_BLOCK_BASE
 */

#define MPC107_I2O_BASE		(MPC107_EUMB_BASE + 0x00000)
#define MPC107_DMA_BASE		(MPC107_EUMB_BASE + 0x01000)
#define MPC107_ATU_BASE		(MPC107_EUMB_BASE + 0x02000)
#define MPC107_I2C_BASE		(MPC107_EUMB_BASE + 0x03000)
#define MPC107_EPIC_BASE	(MPC107_EUMB_BASE + 0x40000)
#define MPC107_DIAG_REGS_BASE	(MPC107_EUMB_BASE + 0x80000)

#define EPIC_BASE	MPC107_EPIC_BASE
#define DIAG_BASE	MPC107_DIAG_REGS_BASE

/* hardware implementation register extensions for MPC107 */

#define HID2	1011		/* HID2 is SPR 1011 */

/* MPC107 Message Unit (I2O) Registers */

#define MPC107_I2O_PIC		(CAST(VUINT8 *)  (MPC107_I2O_BASE + 0x0009))
#define MPC107_I2O_SUB_CLASS	(CAST(VUINT8 *)  (MPC107_I2O_BASE + 0x000a))
#define MPC107_I2O_BASE_CLASS	(CAST(VUINT8 *)  (MPC107_I2O_BASE + 0x000b))
#define MPC107_I2O_IMR0		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0050))
#define MPC107_I2O_IMR1		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0054))
#define MPC107_I2O_OMR0		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0058))
#define MPC107_I2O_OMR1		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x005c))
#define MPC107_I2O_ODBR		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0060))
#define MPC107_I2O_IDBR		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0068))
#define MPC107_I2O_IMISR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0100))
#define MPC107_I2O_IMMR		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0104))
#define MPC107_I2O_IFHPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0120))
#define MPC107_I2O_IFTPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0128))
#define MPC107_I2O_IPHPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0130))
#define MPC107_I2O_IPTPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0138))
#define MPC107_I2O_OFHPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0140))
#define MPC107_I2O_OFTPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0148))
#define MPC107_I2O_OPHPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0150))
#define MPC107_I2O_OPTPR	(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0158))
#define MPC107_I2O_MUCR		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0164))
#define MPC107_I2O_QBAR		(CAST(VUINT32 *) (MPC107_I2O_BASE + 0x0170))

/* MPC107 DMA Registers */

#define MPC107_DMA_0_MODE	(CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0100))
#define MPC107_DMA_0_STATUS	(CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0104))
#define MPC107_DMA_0_ADR_DESC	(CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0108))
#define MPC107_DMA_0_SRC_ADR	(CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0110))
#define MPC107_DMA_0_DEST_ADR	(CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0118))
#define MPC107_DMA_0_BYTE_CNT	(CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0120))
#define MPC107_DMA_0_NSER_ADR	(CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0124))
#define MPC107_DMA_1_MODE       (CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0200))
#define MPC107_DMA_1_STATUS     (CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0204))
#define MPC107_DMA_1_ADR_DESC   (CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0208))
#define MPC107_DMA_1_SRC_ADR    (CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0210))
#define MPC107_DMA_1_DEST_ADR   (CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0218))
#define MPC107_DMA_1_BYTE_CNT   (CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0220))
#define MPC107_DMA_1_NSER_ADR   (CAST(VUINT32 *) (MPC107_DMA_BASE + 0x0224))

/* MPC107 Address Tranlation Unit (ATU) Registers */

#define MPC107_ATU_OMBAR	(CAST(VUINT32 *) (MPC107_ATU_BASE + 0x0300))
#define MPC107_ATU_OTWR		(CAST(VUINT32 *) (MPC107_ATU_BASE + 0x0308))
#define MPC107_ATU_ITWR		(CAST(VUINT32 *) (MPC107_ATU_BASE + 0x0310))

/* MPC107 I2C Registers */

#define MPC107_I2C_ADR_REG	(CAST(VUINT32 *) (MPC107_I2C_BASE + 0x0000))
#define MPC107_I2C_FREQ_DIV_REG	(CAST(VUINT32 *) (MPC107_I2C_BASE + 0x0004))
#define MPC107_I2C_CONTROL_REG	(CAST(VUINT32 *) (MPC107_I2C_BASE + 0x0008))
#define MPC107_I2C_STATUS_REG	(CAST(VUINT32 *) (MPC107_I2C_BASE + 0x000c))
#define MPC107_I2C_DATA_REG	(CAST(VUINT32 *) (MPC107_I2C_BASE + 0x0010))

/* MPC107 EPIC Registers */

#define EPIC_FEATURE_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01000))
#define EPIC_GLOBAL_CONFIG_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01020))
#define EPIC_INTR_CONFIG_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01030))
#define EPIC_VENDOR_ID_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01080))
#define EPIC_PROCESSOR_INIT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01090))
#define EPIC_SPUR_VEC_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x010e0))

#define EPIC_TIMER_FREQ_REG		(CAST(VUINT32 *)(EPIC_BASE + 0x010f0))

#define EPIC_TIMER0_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01100))
#define EPIC_TIMER0_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01110))
#define EPIC_TIMER0_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01120))
#define EPIC_TIMER0_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01130))

#define EPIC_TIMER1_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01140))
#define EPIC_TIMER1_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01150))
#define EPIC_TIMER1_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01160))
#define EPIC_TIMER1_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01170))

#define EPIC_TIMER2_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01180))
#define EPIC_TIMER2_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01190))
#define EPIC_TIMER2_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011a0))
#define EPIC_TIMER2_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011b0))

#define EPIC_TIMER3_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011c0))
#define EPIC_TIMER3_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011d0))
#define EPIC_TIMER3_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011e0))
#define EPIC_TIMER3_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011f0))

#define EPIC_SER_SRC0_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10200))
#define EPIC_SER_SRC0_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10210))

#define EPIC_SER_SRC1_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10220))
#define EPIC_SER_SRC1_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10230))

#define EPIC_SER_SRC2_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10240))
#define EPIC_SER_SRC2_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10250))

#define EPIC_SER_SRC3_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10260))
#define EPIC_SER_SRC3_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10270))

#define EPIC_SER_SRC4_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10280))
#define EPIC_SER_SRC4_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10290))

#define EPIC_SER_SRC5_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x102a0))
#define EPIC_SER_SRC5_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x102b0))

#define EPIC_SER_SRC6_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x102c0))
#define EPIC_SER_SRC6_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x102d0))

#define EPIC_SER_SRC7_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x102e0))
#define EPIC_SER_SRC7_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x102f0))

#define EPIC_SER_SRC8_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10300))
#define EPIC_SER_SRC8_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10310))

#define EPIC_SER_SRC9_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10320))
#define EPIC_SER_SRC9_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10330))

#define EPIC_SER_SRC10_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10340))
#define EPIC_SER_SRC10_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10350))

#define EPIC_SER_SRC11_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10360))
#define EPIC_SER_SRC11_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10370))

#define EPIC_SER_SRC12_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10380))
#define EPIC_SER_SRC12_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10390))

#define EPIC_SER_SRC13_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x103a0))
#define EPIC_SER_SRC13_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x103b0))

#define EPIC_SER_SRC14_VEC_PRI_REG 	(CAST(VUINT32 *) (EPIC_BASE + 0x103c0))
#define EPIC_SER_SRC14_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x103d0))

#define EPIC_SER_SRC15_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x103e0))
#define EPIC_SER_SRC15_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x103f0))

#define EPIC_I2C_INTR_VEC_SRC		(CAST(VUINT32 *) (EPIC_BASE + 0x11020))
#define EPIC_I2C_INTR_DEST		(CAST(VUINT32 *) (EPIC_BASE + 0x11030))

#define EPIC_DMA_CHAN0_INTR_VEC_SRC	(CAST(VUINT32 *) (EPIC_BASE + 0x11040))
#define EPIC_DMA_CHAN0_INTR_DEST	(CAST(VUINT32 *) (EPIC_BASE + 0x11050))

#define EPIC_DMA_CHAN1_INTR_VEC_SRC	(CAST(VUINT32 *) (EPIC_BASE + 0x11060))
#define EPIC_DMA_CHAN1_INTR_DEST	(CAST(VUINT32 *) (EPIC_BASE + 0x11070))

#define EPIC_MSG_UNIT_INTR_VEC_SRC	(CAST(VUINT32 *) (EPIC_BASE + 0x110c0))
#define EPIC_MSG_UNIT_INTR_DEST		(CAST(VUINT32 *) (EPIC_BASE + 0x110d0))

#define EPIC_CUR_TASK_PRI_REG 		(CAST(VUINT32 *) (EPIC_BASE + 0x20080))

#define EPIC_IACK_REG			(CAST(VUINT32 *) (EPIC_BASE + 0x200a0))

#define EPIC_EOI_REG			(CAST(VUINT32 *) (EPIC_BASE + 0x200b0))

/* MPC107 Diagnostic Registers */

#define MPC107_DIAG_WP_DH_REG		(CAST(VUINT32 *) (DIAG_BASE + 0x7f00c))
#define MPC107_DIAG_WP_DL_REG		(CAST(VUINT32 *) (DIAG_BASE + 0x7f010))
#define MPC107_DIAG_WP_PAR_REG		(CAST(VUINT32 *) (DIAG_BASE + 0x7f014))
#define MPC107_DIAG_WP1_CNTL_TRIG	(CAST(VUINT32 *) (DIAG_BASE + 0x7f018))
#define MPC107_DIAG_WP1_ADDR_TRIG	(CAST(VUINT32 *) (DIAG_BASE + 0x7f01c))
#define MPC107_DIAG_WP1_CTRL_MASK	(CAST(VUINT32 *) (DIAG_BASE + 0x7f020))
#define MPC107_DIAG_WP1_ADDR_MASK	(CAST(VUINT32 *) (DIAG_BASE + 0x7f024))
#define MPC107_DIAG_WP1_CTRL_MON	(CAST(VUINT32 *) (DIAG_BASE + 0x7f028))
#define MPC107_DIAG_WP1_ADDR_MON	(CAST(VUINT32 *) (DIAG_BASE + 0x7f02c))
#define MPC107_DIAG_WP2_CNTL_TRIG	(CAST(VUINT32 *) (DIAG_BASE + 0x7f030))
#define MPC107_DIAG_WP2_ADDR_TRIG	(CAST(VUINT32 *) (DIAG_BASE + 0x7f034))
#define MPC107_DIAG_WP2_CTRL_MASK	(CAST(VUINT32 *) (DIAG_BASE + 0x7f038))
#define MPC107_DIAG_WP2_ADDR_MASK	(CAST(VUINT32 *) (DIAG_BASE + 0x7f03c))
#define MPC107_DIAG_WP2_CTRL_MON	(CAST(VUINT32 *) (DIAG_BASE + 0x7f040))
#define MPC107_DIAG_WP2_ADDR_MON	(CAST(VUINT32 *) (DIAG_BASE + 0x7f044))
#define MPC107_DIAG_WPM_CONTROL		(CAST(VUINT32 *) (DIAG_BASE + 0x7f048))

/* MPC107 Configuration Registers */

#define MPC107_CFG_VENDOR_ID		0x00	/* vendor ID = 0x1057 */
#define MPC107_CFG_DEVICE_ID		0x02	/* device ID = 0x0003 */
#define MPC107_CFG_COMMAND		0x04	/* PCI command register */
#define MPC107_CFG_STATUS		0x06	/* PCI status register */
#define MPC107_CFG_REVISION		0x08	/* revision identifier */
#define MPC107_CFG_PROGRAMMING_IF	0x09	/* standard programming intf */
#define MPC107_CFG_SUBCLASS		0x0a	/* subclass code */
#define MPC107_CFG_CLASS		0x0b	/* class code */
#define MPC107_CFG_CACHE_LINE_SIZE	0x0c	/* cache line size */
#define MPC107_CFG_LATENCY_TIMER	0x0d	/* latency timer */
#define MPC107_CFG_HEADER_TYPE		0x0e	/* header type */
#define MPC107_CFG_BIST			0x0f	/* BIST control */
#define MPC107_CFG_DEV_INT_LINE		0x3c	/* interrupt line */