lopec.h

LoPEC Early Access VxWorks BSP

#define PCI_MSTR_CONFIG_DATA_BASE	0xfee00000
#define PCI_MSTR_CONFIG_DATA_SIZE	0x00001000  /* use 4KB page tbl entry */
#define PCI_MSTR_PRIMARY_CDR      	(PCI_MSTR_CONFIG_DATA_BASE + 0xcfc)

#define PCI_MSTR_IACK_BASE_ADRS	0xfef00000  /* PCI interrupt acknowl */
#define PCI_MSTR_IACK_SIZE		0x00001000  /* use 4KB page tbl entry */
#define PCI_MSTR_IACK_WNDW_ADRS	PCI_MSTR_IACK_BASE_ADRS

#define FLASH_BASE_ADRS         0xff000000
#define FLASH_MEM_SIZE          0x01000000

/*
 * PCI MASTER MEMORY WINDOW LIMITS for sysBusProbe
 *
 * These values are strictly defined by the base memory addresses and window
 * sizes of the spaces defined above.  These values must be correct for the
 * sysBusProbe() memory range checks for the PCI bus to work properly.
 */

#define PCI_MSTR_LO_ADRS	PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_HI_ADRS	(PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE)

/* 
 * Map PCI memory access to local CPU space
 *
 * PCI_SLV_MEM_LOCAL  - Base address of Local CPU space
 * PCI_SLV_MEM_BUS    - Base address of local memory as seen from PCI Bus
 * PCI_SLV_MEM_SIZE   - Size of Window for Local space access
 */

/*
 * The macro PCI_SLV_MEM_BUS sets the base value for PCI Mem space access of
 * local memory.  A PCI memory device that puts this address onto the bus will
 * access local memory at the address specified by PCI_SLV_MEM_LOCAL
 */

#define PCI_SLV_MEM_BUS	0x00000000

#define PCI2DRAM_BASE_ADRS	PCI_SLV_MEM_BUS	 /* needed for usrNetwork.c */

/*
 * The macro PCI_SLV_MEM_LOCAL is the base at which local memory will appear
 * in CPU space.
 */

#define PCI_SLV_MEM_LOCAL       LOCAL_MEM_LOCAL_ADRS

/*
 * The macro PCI_SLV_MEM_SIZE specify the range of PCI
 * memory space as it appears on the PCI bus.
 */

#define PCI_SLV_MEM_SIZE	0x40000000	/* CHRP max is 1 GB */

/*
 * PCI Config Space device addresses based on their device number
 *
 * Bit 32 is set to enable CONFIG_DATA accesses to PCI Cycles
 */
     
#define CNFG_PCI_HOST_BRDG      0x80000000 /* IDSEL for PCI host bridge */
#define CNFG_PCI_HOST_BRDG_BUS  0x0	/* Host bridge bus number */
#define CNFG_PCI_HOST_BRDG_DEV	0x0	/* Host bridge device number */
#define CNFG_PCI_HOST_BRDG_FCN	0x0	/* Host bridge function number */

/* Special dec21143 configuration device driver area register */

#define PCI_CFG_21143_DA	0x40

/* PCI Device/Vendor IDs */

#define PCI_ID_I82559           0x12298086      /* Id for Intel 82559 */
#define PCI_ID_I82559ER         0x12098086      /* Id for Intel 82559 ER */
#define PCI_ID_LN_DEC21040      0x00021011      /* Id DEC chip 21040 */
#define PCI_ID_LN_DEC21140      0x00091011      /* Id DEC chip 21140 */
#define PCI_ID_LN_DEC21143      0x00191011      /* Id DEC chip 21143 */
#define PCI_ID_NCR895A          0x00121000      /* Id for SYM53C895A Chip */
#define PCI_ID_SCSI             PCI_ID_NCR895A
#define PCI_ID_IBC              0x056510ad      /* Id for W83C55x PIB */
#define PCI_ID_IDE              0x010510ad      /* Id for W83C55x IDE */

/* PCI to CPU definitions */

#ifdef LOCAL_MEM_AUTOSIZE
#  define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else
#  define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif /* LOCAL_MEM_AUTOSIZE */

/* 
 * System I/O address definitions
 *
 * The system resources are mapped into the lower 1MB address
 * range of FLASH/ROM bank 0 (FFE00000 - FFEFFFFF).
 */

#define LOPEC_SIO_BASE		0xFFE00000     /* base address of system I/O */
#define LOPEC_SIO_SIZE		0x00100000     /* base address of system I/O */

#define LOPEC_SYS_STAT_REG1	(LOPEC_SIO_BASE+0x00000) 
#define LOPEC_SYS_STAT_REG2	(LOPEC_SIO_BASE+0x01000)
#define LOPEC_PCI_PD_REG	(LOPEC_SIO_BASE+0x02000)
#define LOPEC_CONFIG_HDR_REG	(LOPEC_SIO_BASE+0x04000)
#define LOPEC_COM1_UART		(LOPEC_SIO_BASE+0x10000)
#define LOPEC_COM2_UART		(LOPEC_SIO_BASE+0x11000)
#define LOPEC_COM3_UART		(LOPEC_SIO_BASE+0x12000)
#define LOPEC_NVRAM		(LOPEC_SIO_BASE+0x80000)

#define FAIL_LED_ON	(*(UINT8 *)LOPEC_SYS_STAT_REG2 |=  LOPEC_BD_FAIL)
#define FAIL_LED_OFF	(*(UINT8 *)LOPEC_SYS_STAT_REG2 &= ~LOPEC_BD_FAIL)

/* Bit definitions for system status register #1 */

#define LOPEC_RESET		0x80	/* hard reset of board */
#define LOPEC_ABORT		0x10	/* state of the abort signal */
#define LOPEC_EEPROM_WP		0x08	/* EEPROM write protect bit */
#define LOPEC_FLASH_WP		0x04	/* INTEL only, FLASH write protect */
#define LOPEC_FLASH_BSY		0x02	/* AMD only, FLASH device busy */
#define LOPEC_REF_CLK		0x01	/* reference clock */

/* bit definitions for system status register #2 */

#define LOPEC_BD_FAIL		0x80	/* Board fail indicator */
#define LOPEC_LED_1		0x40	/* LED  1 bit, for future use */
#define LOPEC_LED_2             0x20	/* LED  2 bit, for future use */
#define LOPEC_LED_3             0x10    /* LED  3 bit, for future use */
#define LOPEC_LED_4             0x08    /* LED  4 bit, for future use */

/*
 * bit definitions for presence detect register
 * ( A cleared condition means a board is present, a set condition
 *   indicates that no board is present )
 */

#define LOPEC_PRSNT8            0x80    /* 0 = Compact FLASH device present */
#define LOPEC_PRSNT7            0x40    /* 0 = Compact FLASH device present */
#define LOPEC_PRSNT6            0x20    /* not used, always 1 */
#define LOPEC_PRSNT5            0x10    /* not used, always 1 */
#define LOPEC_PRSNT4            0x08    /* not used, always 1 */
#define LOPEC_PRSNT3            0x04    /* 0 = board present in PCI slot 3 */
#define LOPEC_PRSNT2            0x02    /* 0=board present in opt PMC slot 2 */
#define LOPEC_PRSNT1            0x01    /* 0=board present in opt PMC slot 1 */
#define LOPEC_PRSNT_MASK        0xC8    /* mask bits for Presence Detect reg. */

/* Configuration Header register bits */

#define LOPEC_CFG0		0x80	/* 0 = jumper in header position 0 */
#define LOPEC_CFG1              0x40    /* 0 = jumper in header position 1 */
#define LOPEC_CFG2              0x20    /* 0 = jumper in header position 2 */
#define LOPEC_CFG3              0x10    /* 0 = jumper in header position 3 */
#define LOPEC_CFG4              0x08    /* 0 = jumper in header position 4 */
#define LOPEC_CFG5              0x04    /* 0 = jumper in header position 5 */
#define LOPEC_CFG6              0x02    /* 0 = jumper in header position 6 */
#define LOPEC_CFG7              0x01    /* 0 = jumper in header position 7 */

/* 
 * The total size of PCI memory space available with the MPC107 is
 * 2GB - 24MB = 0x7e000000.  The space begins at 0x80000000 =
 * PCI_MSTR_MEMIO_LOCAL.  We reserve the last 1MB (0x100000) of this
 * space for the MPC107 registers - also known as the "Embedded Utilities
 * Memory Block (EUMB)".  The MPC107_REGISTERS_BASE defines the beginning
 * address of this block.
 */

#define MPC107_REGISTERS_BASE  (PCI_MSTR_MEMIO_LOCAL + 0x7cf00000)

/* programmable interrupt controller (PIC) */

#define	PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */

/* programmable interrupt timers */

#define PIT_BASE_ADR		SL82565_TMR1_CNT0	/* timeraddrs */
#define PIT_REG_ADDR_INTERVAL	1
#define PIT_CLOCK		1193180

/* serial ports (COM1, COM2, COM3) */

#define COM1_BASE_ADR		LOPEC_COM1_UART   /* serial port 1 */
#define COM2_BASE_ADR		LOPEC_COM2_UART	  /* serial port 2 */
#define COM3_BASE_ADR		LOPEC_COM3_UART   /* serial port 3 */
#define UART_REG_ADDR_INTERVAL  1       	  /* addr differential */
#define N_UART_CHANNELS 	3		  /* No. serial I/O chans */
#define N_SIO_CHANNELS          N_UART_CHANNELS   /* No. serial I/O chans */

/* INTERRUPT DEFINES */

#define INT_NUM_IRQ0            	INT_VEC_IRQ0

/*
 * EPIC and PIC interrupt sources:
 * 16 ISA interrupts sources from 8259, routed to EPIC #0
 * 16 External Serial interrupt sources EPIC #0-0xF
 * 4 Timer (internal) interrupts
 * 3 Internal interrupts (I2c,DMA0 & DMA 1)
 * 1 Messeage Unit (internal) interrupt
 */

#define EPIC_INTERRUPT_BASE		0x00
#define ISA_INTERRUPT_BASE		(EPIC_INTERRUPT_BASE)
#define	SERIAL_INTERRUPT_BASE		(ISA_INTERRUPT_BASE + 0x10)
#define TIMER_INTERRUPT_BASE		(SERIAL_INTERRUPT_BASE + 0x10)
#define INTERNAL_INTERRUPT_BASE		(TIMER_INTERRUPT_BASE + 0x04)
#define MESSAGE_UNIT_INTERRUPT_BASE     (INTERNAL_INTERRUPT_BASE + 0x03)

#define IS_ISA_INTERRUPT_LEVEL(x) \
	((x >= ISA_INTERRUPT_BASE) && (x < ISA_INTERRUPT_BASE + 0x10))

/* interrupt Level definitions */

/* EPIC Timers */

/* EPIC timer 0 interrupt level */
#define TIMER0_INT_LVL		( 0x0 + TIMER_INTERRUPT_BASE )

/* EPIC timer 1 interrupt level */
#define TIMER1_INT_LVL		( 0x1 + TIMER_INTERRUPT_BASE )

/* EPIC timer 2 interrupt level */
#define TIMER2_INT_LVL		( 0x2 + TIMER_INTERRUPT_BASE )

/* EPIC timer 3 interrupt level */
#define TIMER3_INT_LVL		( 0x3 + TIMER_INTERRUPT_BASE )

/* External interrupt sources */

/* PIB interrupt level for interrupts coming from the 8259 PIC */
#define PIB_INT_LVL             ( 0x00 + SERIAL_INTERRUPT_BASE )

/* ethernet interrupt level */
#define LN_INT_LVL		( 0x01 + SERIAL_INTERRUPT_BASE )

/* 16550 UART interrupt level (COM port 2 & 3) */
#define COM2_INT_LVL		( 0x04 + SERIAL_INTERRUPT_BASE )
#define COM3_INT_LVL		( 0x05 + SERIAL_INTERRUPT_BASE )

/* SCSI interrupt level */
#define SCSI_INT_LVL		( 0x06 + SERIAL_INTERRUPT_BASE )

/* PCI expansion INTA */
#define PCI_INTA_LVL		( 0x07 + SERIAL_INTERRUPT_BASE )

/*  PCI expansion INTB */
#define PCI_INTB_LVL		( 0x08 + SERIAL_INTERRUPT_BASE )

/* PCI expansion INTC */
#define PCI_INTC_LVL		( 0x09 + SERIAL_INTERRUPT_BASE )

/* PCI expansion INTD */
#define PCI_INTD_LVL		( 0x0a + SERIAL_INTERRUPT_BASE )

/* USB interrupt level */
#define USB_INT_LVL		( 0x0b + SERIAL_INTERRUPT_BASE )

/* 16550 UART interrupt level (COM port 1) */
#define COM1_INT_LVL		( 0x0d + SERIAL_INTERRUPT_BASE )

/* front panel abort switch */
#define ABORT_INT_LVL		( 0x0e + SERIAL_INTERRUPT_BASE )

/* RTC (watchdog/alarm) */
#define RTC_INT_LVL		( 0x0f + SERIAL_INTERRUPT_BASE )

/* EPIC internal interrupts */

/* MPC107 I2C interrupt */
#define I2C_INT_LVL		(0x00 + INTERNAL_INTERRUPT_BASE )

/* EPIC DMA #0 */
#define DMA0_INT_LVL		(0x01 + INTERNAL_INTERRUPT_BASE )

/* EPIC DMA #1 */
#define DMA1_INT_LVL		(0x02 + INTERNAL_INTERRUPT_BASE )

/* EPIC Message Unit */
#define MESSAGE_UNIT_INT_LVL	(0x00 + MESSAGE_UNIT_INTERRUPT_BASE )

/* interrupt vector definitions */

#define INT_VEC_IRQ0            0x00    /* vector for IRQ0 */

/* IDE Interrupt defines */

#ifdef INCLUDE_ATA
/* IDE controller interrupt level */

#   define IDE_CNTRLR0_INT_LVL ( 0x0e + ISA_INTERRUPT_BASE )
#   define IDE_CNTRLR1_INT_LVL ( 0x0f + ISA_INTERRUPT_BASE )

/* IDE interrupt vectors */

#   define IDE_CNTRLR0_INT_VEC  ( INT_VEC_IRQ0 + IDE_CNTRLR0_INT_LVL )
#   define IDE_CNTRLR1_INT_VEC  ( INT_VEC_IRQ0 + IDE_CNTRLR1_INT_LVL )
#endif  /* INCLUDE_ATA */

/* LoPEC interrupt vector definitions */

#define LN_INT_VEC		INT_VEC_IRQ0 + LN_INT_LVL
#define	PCI_INTA_VEC		INT_VEC_IRQ0 + PCI_INTA_LVL
#define	PCI_INTB_VEC		INT_VEC_IRQ0 + PCI_INTB_LVL
#define	PCI_INTC_VEC		INT_VEC_IRQ0 + PCI_INTC_LVL
#define	PCI_INTD_VEC		INT_VEC_IRQ0 + PCI_INTD_LVL
#define COM1_INT_VEC		INT_VEC_IRQ0 + COM1_INT_LVL
#define COM2_INT_VEC		INT_VEC_IRQ0 + COM2_INT_LVL
#define COM3_INT_VEC		INT_VEC_IRQ0 + COM3_INT_LVL
#define SCSI_INT_VEC		INT_VEC_IRQ0 + SCSI_INT_LVL
#define USB_INT_VEC		INT_VEC_IRQ0 + USB_INT_LVL
#define ABORT_INT_VEC		INT_VEC_IRQ0 + ABORT_INT_LVL
#define RTC_INT_VEC		INT_VEC_IRQ0 + RTC_INT_LVL
#define TIMER0_INT_VEC		INT_VEC_IRQ0 + TIMER0_INT_LVL
#define TIMER1_INT_VEC          INT_VEC_IRQ0 + TIMER1_INT_LVL
#define TIMER2_INT_VEC          INT_VEC_IRQ0 + TIMER2_INT_LVL
#define TIMER3_INT_VEC          INT_VEC_IRQ0 + TIMER3_INT_LVL
#define PIB_INT_VEC             INT_VEC_IRQ0 + PIB_INT_LVL

/*
 * Address range definitions for PCI buses.
 *
 * Used with vxMemProbe() hook sysBusProbe().
 */

#define IS_PCI_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)PCI_MSTR_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)PCI_MSTR_HI_ADRS))

/*
 * Support for determining if we're ROM based or not.  _sysInit
 * saves the startType parameter at location ROM_BASED_FLAG.
 */

#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
				     PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )

/* Translation macro */
 
#define TRANSLATE(x,y,z)\
        ((UINT)(x) - (UINT)(y) + (UINT)(z))
 
#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* INClopech */