lopec.h

LoPEC Early Access VxWorks BSP

/* lopec.h - Motorola PowerChap board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01t,24apr01,cak  added MEM_REFRESH_DELAY define
01s,13feb01,cak  Added and modified defines for MT48T37Y (RTC/NVRAM chip)
01r,08feb01,cak  Modified and added defines for COM2 and COM3
01q,07feb01,cak  Added ULTRA2_SCSI define, moved from config.h
01p,06feb01,cak  Added SCSI Support
01o,02feb01,scb  remvoved shared memory related infomation
01n,26jan01,scb  Added requiried defines for L2 cache on MAX (MPC7400).
01m,18jan01,scb  Modified for MPC107 address map B (CHRP)
01l,15jan01,djs  Add ROM_SPEED define
01k,04jan01,scb  make FAIL_LED_[ON|OFF] macros
01j,02jan01,cak  Added IDE/ATA support
01i,18dec00,djs  changed SPEED66MHZ to SPEED67MHZ
01h,13dec00,djs  Cleanup/rename macros
01g,08dec00,djs  changes for VPD and i2c support
01f,30nov00,djs  support for i82559
01e,20nov00,scb  Non-romInit.s processor support
01d,17nov00,djs  Changes interrupt base defines
01c,14nov00,scb  Changes for "romInit.s" processor support
01b,09nov00,djs  Changes based on mods to sysBusPci.c
01a,02nov00,djs  Created from 01q,15jun00,dmw (mv2100.h)
*/

/*
This file contains I/O addresses and related constants for the
Motorola PowerChap ATX board. 
*/

#ifndef	INClopech
#define	INClopech

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

#include "mpc107.h"

/* MPC7400 (Max) Support */

/* AltiVec Exceptions */

#define _EXC_VMX_UNAVAIL       0x0f20	/* VMX Unavailable Exception */
#define _EXC_VMX_ASSIST        0x1600	/* VMX Assist Exception */
#define SIZEOF_EXCEPTION       0x0030	/* VxWorks Exc is 48 bytes Max*/

/* L2 cache support */

#ifdef INCLUDE_CACHE_SUPPORT
#   define INCLUDE_CACHE_L2
#else
#   undef INCLUDE_CACHE_L2
#endif

/* ATA/EIDE support */

#ifdef INCLUDE_ATA
#   include "drv/pcmcia/pccardLib.h"
#   include "drv/hdisk/ataDrv.h"
#endif  /* INCLUDE_ATA */

/*
 * SCSI Support
 *
 *   INCLUDE_SCSI2: Provides the device independent SCSI interface.
 * INCLUDE_SYM_895: Provides support for the Symbios/LSI Logic SYM53C895A
 *                  PCI to Ultra2 SCSI controller.
 *     ULTRA2_SCSI: Configures the SYM53C895A for Ultra2 SCSI support.
 */

#ifdef INCLUDE_SCSI
#   define INCLUDE_SCSI2        /* Include the SCSI2 library */
#   define INCLUDE_SYM_895      /* Symbios/LSI Logic SYM53C895A Support */
#   define ULTRA2_SCSI		/* Ultra2 SCSI Support */
#endif  /* INCLUDE_SCSI */

/* Real-time clock and Alarm clock Support */

#ifdef INCLUDE_RTC 
#   define RTC_SET(x)			m48t37RtcSet (x)
#   define RTC_SHOW()      		m48t37RtcShow ()
#   define RTC_GET(x)      		m48t37RtcGet (x)
#   define RTC_DATE_TIME_HOOK(x)	m48t37DateTimeHook (x)
#   define ALARM_SET(x,y)		m48t37AlarmSet (x,y) 
#   define ALARM_CANCEL()		m48t37AlarmCancel ()
#   define ALARM_GET(x,y)		m48t37AlarmGet (x,y) 
#   define ALARM_SHOW()			m48t37AlarmShow () 
#endif /* INCLUDE_RTC */

/* Failsafe Timer Support */

#ifdef INCLUDE_FAILSAFE
#   define FAILSAFE_SET(x,y)		m48t37FailsafeSet (x,y)
#   define FAILSAFE_GET(x,y)		m48t37FailsafeGet (x,y) 
#   define FAILSAFE_CANCEL()		m48t37FailsafeCancel ()
#   define FAILSAFE_SHOW()		m48t37FailsafeShow ()
#   define FAILSAFE_CAUSED_RESET()	m48t37FailsafeCausedReset ()
#endif /* INCLUDE_FAILSAFE */

/* CPU type */

#define CPU_TYPE		((vxPvrGet() >> 16) & 0xffff)
#define CPU_REV			(vxPvrGet() & 0xffff)
#define CPU_TYPE_601		0x01	/* PPC 601 CPU */
#define CPU_TYPE_602		0x02	/* PPC 602 CPU */
#define CPU_TYPE_603		0x03	/* PPC 603 CPU */
#define CPU_TYPE_603E		0x06	/* PPC 603e CPU */
#define CPU_TYPE_603P		0x07	/* PPC 603p CPU */
#define CPU_TYPE_750		0x08	/* PPC 750 CPU */
#define CPU_TYPE_604		0x04	/* PPC 604 CPU */
#define CPU_TYPE_604E		0x09	/* PPC 604e CPU */
#define CPU_TYPE_604R		0x0A	/* PPC 604r CPU */
#define CPU_TYPE_MAX		0x0C    /* PPC MAX CPU */
#define CPU_TYPE_NITRO		0x800C	/* PPC NITRO CPU */
#define CPU_REV_NITRO		0x1100	/* PPC Nitro Rev 1.0 CPU */

/* Vital Product Data Support */

#define NUM_SDRAM_BANKS		4	/* Number of possible SDRAM banks */
#define SPD_EEPROM_ADRS0	0xa0	/* i2c address of first SPD EEPROM */

#define VPD_BRD_EEPROM_ADRS	0xa8	/* i2c address of board's SROM */

#define VPD_BRD_OFFSET		0	/* offset into board's eeprom for 
					   vpd data */
#define EEPROM_TYPE_MPC107	0
#define I2C_DRV_TYPE		EEPROM_TYPE_MPC107 /* I2C driver type flag */
#define VPD_PKT_LIMIT		25	/* Max number of packets expected */

#define DEFAULT_PCI_CLOCK	33333333
#define DEFAULT_BUS_CLOCK	100000000
#define DEFAULT_INTERNAL_CLOCK	250000000
#define DEFAULT_PRODUCT_ID	"Unknown"

#define MHZ	    		1000000
#define NANO2SEC    		1000000000  /* num of nanoseconds per second */

#define ROM_SPEED 180		/* ROM bank access speed (ns) */

#define INCLUDE_PCI		/* always include pci */

/* 
 * Non-volatile (NVRAM) defines.
 * NVRAM/RTC is located between FFE80000 and FFE87FFF (32K)
 * The first 256 bytes are skipped, the second 256 bytes are used to
 * store the vxWorks boot line parameters.
 * 16 bytes, from FFE87FF0 to FFE87FFF are used for the M48T37Y registers
 * The NVRAM_BASE address is used in the sysNvWrite and sysNvRead
 * routines in sysLib.c.  In order to write to/read from NVRAM you
 * need only specify an offset. (ie. NVRAM_BASE + offset)
 */

#undef	NV_BOOT_OFFSET
#define NV_BOOT_OFFSET		256 	/* skip 1st 256 bytes */
#define NV_RAM_SIZE    		0x7FF0	/* 32KB Total-16Bytes for registers */	
#define NV_RAM_ADRS    		LOPEC_NVRAM     /* Beginning of NVRAM */	
#define NV_RAM_INTRVL           1       /* Address interval between bytes */
#define NVRAM_BASE		LOPEC_NVRAM	/* NVRAM base address */
#define NV_RAM_READ(x)		sysNvRead (x)
#define NV_RAM_WRITE(x,y)	sysNvWrite (x,y)

/* PCI I/O function defines */

#ifndef _ASMLANGUAGE

#ifndef PCI_IN_BYTE
#   define PCI_IN_BYTE(x)          sysPciInByte (x)
    IMPORT  UINT8                  sysPciInByte  (UINT32 address);
#endif /* PCI_IN_BYTE */
#ifndef PCI_IN_WORD
#   define PCI_IN_WORD(x)          sysPciInWord (x)
    IMPORT  UINT16                 sysPciInWord  (UINT32 address);
#endif /* PCI_IN_WORD */
#ifndef PCI_IN_LONG
#   define PCI_IN_LONG(x)          sysPciInLong (x)
    IMPORT  UINT32                 sysPciInLong  (UINT32 address);
#endif /* PCI_IN_LONG */
#ifndef PCI_OUT_BYTE
#   define PCI_OUT_BYTE(x,y)       sysPciOutByte (x,y)
    IMPORT  void                   sysPciOutByte (UINT32 address, UINT8  data);
#endif /* PCI_OUT_BYTE */
#ifndef PCI_OUT_WORD
#   define PCI_OUT_WORD(x,y)       sysPciOutWord (x,y)
    IMPORT  void                   sysPciOutWord (UINT32 address, UINT16 data);
#endif /* PCI_OUT_WORD */
#ifndef PCI_OUT_LONG
#   define PCI_OUT_LONG(x,y)       sysPciOutLong (x,y)
    IMPORT  void                   sysPciOutLong (UINT32 address, UINT32 data);
#endif /* PCI_OUT_WORD */

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 32 32-bit value = 128 bytes */

#define PCI_CLINE_SZ		0x20

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/* clock rates */

#define SPEED67MHZ		67
#define SPEED83MHZ		83
#define SPEED100MHZ		100

/* Calculate Memory Bus Rate in Hertz */

#define MEMORY_BUS_SPEED        (sysGetBusSpd())

/* System clock (decrementer counter) frequency determination */

#define DEC_CLOCK_FREQ          MEMORY_BUS_SPEED

/* CIO clocks and stuff */

#define	CIO_RESET_DELAY		5000
#define	ZCIO_HZ			2500000 /* 2.5 MHz clock */
#define	CIO_INT_VEC		9
#define	Z8536_TC		ZCIO_HZ

/*
 * The PowerPC Decrementer is used as the system clock.
 * It is always included in this BSP.  The following defines
 * are used by the system clock library.
 */

#define SYS_CLK_RATE_MIN  	10		/* minimum system clock rate */
#define SYS_CLK_RATE_MAX  	5000		/* maximum system clock rate */

/*
 * The following define is used in romInit.s in the waitRefresh routine
 * as the number of clocks to delay, after configuring the MPC107 memory
 * controller, before turning the memory controller back on. The delay
 * allows a memory refresh to occur, and must be at least 200 microseconds
 * (.0002 seconds).
 * Assume the fastest lopec clock (100MHz), 100MHz = 100,000,000 Hz or
 * clock cycles/second, and that the decrementer in the routine counts down
 * 1 value in 4 clock cycles. 
 *
 *        100,000,000 * .0002 = 20,000 clock cycles
 *        20,000/4 = 5000 clocks
 */

#define MEM_REFRESH_DELAY	5000		/* 200 microsecond delay */

/*
 * This macro returns the positive difference between two signed ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)		( abs((int)a - (int)b) )

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.  The following defines are used by the aux clock library.
 */

#define AUX_CLK_RATE_MIN  	40		/* min auxiliary clock */
#define AUX_CLK_RATE_MAX	5000		/* max auxiliary clock rate */

/* 
 * Common I/O synchronizing instructions 
 *
 * Only SYNC is used for the 603e processors.  The "eieio" instruction
 * is treated as a NOP on the 603e.
 */

#ifndef SYNC
#  define SYNC  		__asm__ volatile ("sync")
#endif  /* SYNC */

/* BSP configuration error policy */

#define CONTINUE_EXECUTION      0       /* Tolerate VPD/Configuration errors */
#define EXIT_TO_SYSTEM_MONITOR  1       /* Transfer to System Monitor */

#ifdef TOLERATE_CONFIG_ERRORS
#  define DEFAULT_BSP_ERROR_BEHAVIOR  CONTINUE_EXECUTION
#else
#  define DEFAULT_BSP_ERROR_BEHAVIOR  EXIT_TO_SYSTEM_MONITOR
#endif /* TOLERATE_CONFIG_ERRORS */

/* 
 * The following macros define access to PCI I/O and Memory spaces.
 * Those macros with "LOCAL" in their name refer to local processor
 * addresses.  Those with "BUS" in their name refer to PCI bus
 * addresses.
 */

/* First the PCI I/O space access macros: */

/*
 * Access to 16-bit PCI ISA I/O space:
 * Note that the lowest 0x4000 bytes (ISA_LEGACY_SIZE) of this space is
 * the static ISA space and is not configured by the PCI autoconfiguration
 * function.  The space above this is the dynamically configured 16-bit
 * PCI I/O space and is handled by the PCI autoconfiguration function.
 */

#define ISA_MSTR_IO_LOCAL	0xfe000000	/* local processor address */
#define ISA_MSTR_IO_BUS		0x00000000      /* PCI bus 0 based addressing */
#define ISA_LEGACY_SIZE 	0x00004000	/* For staic ISA space only */
#define ISA_MSTR_IO_SIZE 	0x00010000      /* Total 16-bit I/O size */

/* Access to 32-bit PCI I/O space:
 * The size of this space is goverened by PCI_MSTR_IO_SIZE
 * which is a user configurable parameter and appears in "config.h"
 */

#define PCI_MSTR_IO_LOCAL	0xfe800000	/* local processor address */
#define PCI_MSTR_IO_BUS		0x00800000	/* PCI bus address */

/* Now for the PCI memory space macros */

/*
 * Access to nonprefetchable PCI memory space:
 * The size of this space is goverened by PCI_MSTR_MEMIO_SIZE
 * which is a user configurable parameter and appears in "config.h"
 */

#define PCI_MSTR_MEMIO_LOCAL	0x80000000
#define PCI_MSTR_MEMIO_BUS	PCI_MSTR_MEMIO_LOCAL	/* 1-1 translation */

/*
 * Access to prefetchable PCI memory space:
 * The size of this space is goverened by PCI_MSTR_MEM_SIZE
 * which is a user configurable parameter and appears in "config.h"
 */

#define PCI_MSTR_MEM_LOCAL    (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_BUS      PCI_MSTR_MEM_LOCAL	/* 1-1 translation */

/* For PCI configuration access */

#define PCI_MSTR_CONFIG_ADDR_BASE	0xfec00000
#define PCI_MSTR_CONFIG_ADDR_SIZE	0x00002000  /* use 4KB page tbl entry */
#define PCI_MSTR_PRIMARY_CAR      	(PCI_MSTR_CONFIG_ADDR_BASE + 0xcf8)