config.h

LoPEC Early Access VxWorks BSP

#define LOCAL_MEM_SIZE		0x02000000	/* Default: Min memory: 32MB */

#define RAM_HIGH_ADRS		0x00800000  	/* RAM address for ROM boot */
#define RAM_LOW_ADRS		0x00100000	/* RAM address for kernel */

/* user reserved memory, see sysMemTop() */

#define USER_RESERVED_MEM	(0)	/* number of reserved bytes */

#define	FLASH_TEXT_ADRS	(FLASH_BASE_ADRS + 0x100) /* 0xff000100 */

/*
 * The constants ROM_SIZE, RAM_LOW_ADRS and RAM_HIGH_ADRS 
 * are defined in config.h, Makefile.
 * All definitions for these constants must be identical.
 */

#ifdef  FLASH_BOOT
#    define	ROM_BASE_ADRS	FLASH_BASE_ADRS	 /* base address of flash */
#    define	ROM_TEXT_ADRS	FLASH_TEXT_ADRS
#else
#   define	ROM_BASE_ADRS	0xfff00000	/* base addr of socketed ROM */
#   define	ROM_TEXT_ADRS	(ROM_BASE_ADRS + 0x100)
#endif /* FLASH_BOOT */


#define	ROM_SIZE		0x00100000	/* 1 Meg ROM space */

/* Setup the sizes of the various PCI window spaces */

/*
 * PCI_MSTR_IO_SIZE
 * Total size of the PCI 32-bit I/O space.  The maximum value
 * permitted by the MPC107 for this parameter is 4MB (0x00400000).
 */

#define PCI_MSTR_IO_SIZE        0x00400000      /* 4MB window by default */

/*
 * PCI_MSTR_MEMIO_SIZE
 * Size of the PCI nonprefetchable memory space available to the
 * PCI autoconfiguration function.  Note that at least 64MB is needed
 * using PCI-PCI bridging.  Also the sum of PCI_MSTR_MEMIO_SIZE and 
 * PCI_MSTR_MEM_SIZE cannot exceed  2GB - 32MB = 0x7e000000.
 */

#define PCI_MSTR_MEMIO_SIZE     0x04000000      /* 64MB default */

/*
 * PCI_MSTR_MEM_SIZE
 * Size of the prefetchable PCI memory space available to the
 * PCI autoconfiguration function.  See PCI_MSTR_MEMIO_SIZE for
 * restrictions of the size of this parameter.
 */

#define PCI_MSTR_MEM_SIZE       0x00800000      /* 8MB default */

/*
 * These defines are used to initialize the External Source
 * Vector/Priority registers in the EPIC.  The following can
 * be defined: interrupt sensitivity, polarity and interrupt priority.
 *
 * Note: by default a 1 into the sense bit(22) will setup for level
 * sensitive, and a 0 into the polarity bit(23) will setup for low
 * polarity.
 *
 * At initialization all external interrupt sources are disabled.
 *
 * All currently unused interrupt sources are set to a priority of
 * 0, which will not allow them to be enabled.  If any one of these
 * levels is to be used, the priority value must be changed here.
 */
 
#define INIT_SER_SRC0           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  HIGH_POLARITY |\
                                  PRIORITY_LVL3 )   /* PIB */
 
#define INIT_SER_SRC1           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL14 )  /* primary ethernet */
 
#define INIT_SER_SRC2           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  HIGH_POLARITY |\
                                  PRIORITY_LVL0 )  /* not used */
 
#define INIT_SER_SRC3           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )  /* not used */

#define INIT_SER_SRC4           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  HIGH_POLARITY |\
                                  PRIORITY_LVL8 )  /* COM 2 */
 
#define INIT_SER_SRC5           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  HIGH_POLARITY |\
                                  PRIORITY_LVL8 )  /* COM 3 */
 
#ifdef  INCLUDE_SCSI
#define INIT_SER_SRC6           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL3 )  /* SCSI */
#else
#define INIT_SER_SRC6           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )  /* not used */
#endif  /* INCLUDE_SCSI */
 
#define INIT_SER_SRC7           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTA */
 
#define INIT_SER_SRC8           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTB */

#define INIT_SER_SRC9           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTC */

#define INIT_SER_SRC10          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTD */

#define INIT_SER_SRC11          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL3 )   /* USB */
 
#define INIT_SER_SRC12          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */
						    /* perph. parallel ctrl.) */
 
#define INIT_SER_SRC13          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  HIGH_POLARITY |\
                                  PRIORITY_LVL8 )   /* COM1 */
 
#define INIT_SER_SRC14          ( INT_MASK_BIT |\
                                  EDGE_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL4 )  /* abort switch */
 
#define INIT_SER_SRC15          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL5 )   /* RTC */

/* Initial timer values */

#define INIT_TMR_SRC0           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* AUX Clock */

#define INIT_TMR_SRC1           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* off */

#define INIT_TMR_SRC2           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* off */

#define INIT_TMR_SRC3           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* off */

/* Initial DMA interrupt values */

#define INIT_DMA_SRC0           ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

#define INIT_DMA_SRC1           ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

/* Initial I2C interrupt value */

#define INIT_I2C_SRC            ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

/* Initial message unit interrupt value */

#define INIT_MSGUNIT_SRC        ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

/* BSP-specific includes */

#include "lopec.h"


/*
 * This is the IDSEL value for the planar 82559 ethernet interface. 
 * It is intended to be the primary Ethernet device. This BSP has
 * the ability to support a second Ethernet device via a PMC slot
 * or PCI slot. The secondary Ethernet site is sit to IDSEL 16
 * which is PMC slot 1. Other possible IDSEL sites are listed
 * below:
 * PMC slot 1: 16
 * PMC slot 2: 18
 * PCI slot 1: 19
 */
 
#define PCI_IDSEL_PRI_LAN       14
#ifdef  INCLUDE_SECONDARY_ENET
#    define PCI_IDSEL_SEC_LAN       16
#endif /* INCLUDE_SECONDARY_ENET */

#ifdef __cplusplus
}
#endif

#endif	/* INCconfigh */

#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif