target.nr

LoPEC Early Access VxWorks BSP

Real-time and alarm clock support are included in the BSP by defining
INCLUDE_RTC in config.h.  This support by default is excluded.

When the real-time clock information matches the alarm clock settings
an interrupt will be generated.

Once set, the alarm clock will retain its settings upon a board reset.
The real-time and alarm clock support routines are defined in sysRtc.c.

The real-time clock can be set with a call to sysRtcSet().  The following
information needs to be supplied in order to set the RTC: century, year,
month, day of month, day of week, hour, minute, and second.  The current
RTC settings can be retrieved with a call to sysRtcGet().  The current
RTC date and time can be displayed with a call to sysRtcShow().  The
sysRtcDateTimeHook() routine is provided as a hook to the vxWorks dosFsLib
as a means of providing the date and time for file timestamps.

The alarm clock can be programmed in the following five ways: 
.CS 
  Method           Configurable Parameters
 ------------------------------------------------------------
 Once a month      Date, hour, minute, second
 Once a day        Hour, minute, second
 Once an hour      Minute, second
 Once a minute     Second
 Once a second     (none)
.CE

The alarm clock is set with a call to sysAlarmSet().  This routine takes
a method and the alarm clock parameters as arguments.  The alarm clock can
be cancelled with a call to sysAlarmCancel().  The current alarm clock
settings can be retrieved with a call to sysAlarmGet().  The current alarm
clock settings can be displayed with a call to sysAlarmShow().  The routine
sysAlarmIntr() is the alarm clock interrupt handler.  In order to define your 
own interrupt handler, simply edit this routine.

.SS "Boot Devices"
The supported boot devices are:
.CS
    er - Ethernet (10baseT or 100baseTX)

    scsi=<scsi_id#>,<lun#> - SCSI Drive

    ata=<controller number>,<device number> - ATA/IDE Drive

           controller number is:
              0 = 3.5" or 2.5" master/slave device
              1 = Compact Flash device (master only) 
           device number is:
              0 = 3.5" master device or
                  2.5" master device or
                  Compact Flash device
              1 = 3.5" slave device or
                  2.5" slave device
.CE
Note:  By default, with INCLUDE_ATA defined, vxWorks is not set up for any
       devices.  If you have multiple controllers and/or hard disks you must
       modify the ATA_DEVn_STATE defines in config.h to support more drives.

.SS "Boot Methods"
The boot methods are affected by the boot parameters.  If no password is
specified, RSH (remote shell) protocol is used.  If a password is specified,
FTP protocol is used, or, if the flag is set, TFTP protocol is used.

These protocols are used for Ethernet interface.

.SS "ROM Considerations"

LoPEC contains both socketed and soldered flash ROMs.

Socketed flash-ROM appears at address 0xFFF00000.
.sp
Soldered flash-ROM appears at address 0xFF000000.
	
Execution on power-up always begins at 0xFFF00100.  Thus a functioning
board must always have socketed ROM installed at power-up.

The determination as to whether or not to continue to execute out of
socketed flash-ROM or to jump to soldered flash-ROM (0xFF000100) is
controlled by a bit in the configuration header register (1-byte at
address 0xFFE04000) which represents the setting of DIP switch zero.
If the DIP switch is on, the start-up code will jump to soldered
flash-ROM (0xFF000100), if it is off start-up code will continue to
execute out of socketed flash-ROM (0xFFF00100).

Note that the DIP switches are not labeled with numbers.  The diagram
that appears later in this section describes the location of the DIP 
switch which controls
the ROM boot.  The other DIP switches in the bank of 8 have no 
effect on any VxWorks functions.

The state of FLASH_BOOT (#define or #undef) in "config.h" must be set
based upon which type of flash-ROM (soldered or socketed) is to hold
the VxWorks bootrom image.

The default state is for FLASH_BOOT to be #define'd.  This produces a
VxWorks bootrom which will only run out of soldered flash-ROM.  Since
PPC5-Bug runs out of socketed ROM, this makes management of the
VxWorks bootrom convenient (the VxWorks bootrom can be download and
"pflash"ed into soldered flash-ROM with PPC5-Bug).  

It is also possible to #undef FLASH_BOOT and rebuild the VxWorks
bootrom image.  This would create an image which will only run 
out of socketed ROM.  Although this is a possible configuration, it is
not as convenient since the PPC5-Bug will only run out of socketed
flash-ROM and placing the VxWorks bootrom image into socketed
flash-ROM causes complete loss of PPC5-Bug.

Note that PPC5-Bug has been built to run only out of socketed-ROM.
Attempting to move the PPC5-Bug from socketed flash-ROM to soldered
flash-ROM via the "pflash" command will result in a non-functioning
PPC5-Bug.

.CS
	
	X X X X X X X |     
     S1 | | | | | | | |
	| | | | | | | X <-- This is the DIP switch which controls
			    whether we are running from socketed
       (processor side)     or soldered flash.  Set in this
			    position we are running from socketed
			    flash (which contains PPC5-Bug).  This
			    DIP switch is closest to the edge of
			    the board.
	                      
    Here is how the DIP switches looked when running from soldered
    flash, again remember that the board is oriented in such a way
    that the processor is closest to us.
	
	X X X X X X X X <-- Note we have moved this switch.
     S1 | | | | | | | |
	| | | | | | | |

       (processor side)

    The remaining DIP switches play no role in the ROM selection
    processed and their positioning is irrelevant.
	

Use the following command sequence on the host to re-make the BSP boot ROM:

    cd target/config/lopec
    make clean
    make bootrom
    elfToBin < bootrom > boot.bin
    chmod 666 boot.bin
    cp boot.bin /tftpboot/boot.bin
.CE

.SS "Flashing the Soldered Flash-ROM Using Motorola PPC5-Bug:" 

Before you power-up the LoPEC, make sure the DIP switch which selects
socketed flash-ROM or soldered flash-ROM (described above) is properly
set so that PPC5-Bug runs. 

At the PPC5-Bug prompt, start the system clock then set up the network transfer
from a TFTP host using `niot'.  To start the system clock, the \f3set\f1
command must be used.  The format is: set MMDDYYhhmm  where MM is month, DD is
day of month, YY is year, hh is hour (24-hour format), and mm is minutes.  This
command starts the system clock and sets the current date and time.

.CS
   PPC5-Bug>set 1016971302
.CE

Using `niot', the Client IP Address, Server IP Address, and Gateway IP Address
must be set up for the user's specific environment:

.CS
   PPC5-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.213.12.123
   Server IP Address      =123.123.18.105? 123.213.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.213.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC5-Bug>
.CE

The file is transferred from the TFTP host to the target board using
the `niop' command.  Important: You must have a TFTP server running on your
host's subnet for the `niop' command to succeed.  The file name must be set to
the location of the binary file on the TFTP host.  The binary file must be
stored in the directory identified for TFTP accesses, but the file name is
a relative path and does not include the \f3/tftpboot\f1 directory name:

.CS
   PPC5-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? boot.bin
   Memory Address =00004000?
   Length         =00000000?
   Byte Offset    =00000000?

   PPC5-Bug>
.CE

After the file is loaded onto the target, the "pflash" command is used
to put it into soldered flash-ROM:


To put it into soldered FLASH:
.CS
   PPC5-Bug>pflash 4000:fff00 ff000100
.CE

When the command is finished, power down the board, move the DIP switch,
then power the board back up.

The value of FLASH_BOOT in config.h must be set appropriately
for the VxWorks bootrom image being flashed, otherwise the bootrom
will not execute.  See ROM Considerations for more details on setting
up FLASH_BOOT correctly.  Also note that PPC5-Bug has been compiled to
run out of socketed ROM (0xFFF00000).  If it is moved to soldered ROM
with the pflash command it will not function properly.  Thus it is
not possible to move PPC5-Bug to soldered ROM and use it to pflash
the VxWorks bootrom into socket flash.  

IMPORTANT: Do not attempt to pflash VxWorks into the socketed ROM with
PPC5-Bug.  The pflash command will fail and you will destroy the
PPC5-Bug image which resides in socketed ROM, resulting in an unuseable
board.  Use the pflash command only to program VxWorks into the soldered 
ROM as explained above.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information concerning this BSP and its
use.

.SS "Delivered Objects"
The delivered objects are: `boot.bin', `vxWorks', `vxWorks.sym', and 
`vxWorks.st'.

.SS "Make Targets"
The make targets are listed as the names of object-format files.

 `bootrom'
 `bootrom_uncmp'
 `vxWorks' (with `vxWorks.sym')
 `vxWorks.st'
 `vxWorks.st_rom'

.SS "Known Problems"
LoPEC requires PC-100 (or PC-133) SDRAM DIMMs.  Systems using the MPC107
with 66MHz memory bus frequency may use unbuffered DIMMs.  That is, systems
with the MPC750 processor may use unbuffered DIMMs.  Systems with higher
memory bus frequencies (MPC7410) must use registered DIMMs.

.SH "BOARD LAYOUT"
The diagram below shows socketed flash and DIP switch bank configuration:
XU2 and XU1 contain PPC5-Bug.

.ne 4i

.CS
 ____________________________________________________________________
|                      J32  J19   || ||   J28   J27     J23          |
|                       ||   ||   || ||    ||    ||   --------       |
|                       ||   ||  J30 J29   ||    ||   |  -----       |
|                  | |  ||   || COM3 COM2  ||    ||   |  |           |
|                  |2|  ||   ||            ||    ||   |  |           |
|                  ||| SCSI Low            ||    ||   |  |           |
| +----------+     |R|    Density          ||   2.5"  |  -----       |
| || |||||| ||     |O|    Parallel        3.5"  EIDE  --------       |
| |Processor||     |W|      Port          EIDE        Compact Flash  |
| || |||||| ||     | |                                               |
| +----------+     |D|     -------                                   |
|                  |I|     | J15 |                                   |
|                  |M|     -------                                   |
|                  |M|      High                    +----\           |
|                  |S|     Density         S1       |XU2 |           |
|                  | |     Parallel        ::       +----+           |
|                            Port          ::                        |
|                                          ::                        |
|                                          ::       +----\           |
|                                       8-DIP       |XU1 |           |
|                                       switch      +----+           |
|  COM1       er0                       bank                         |
| serial  10/100BaseT                                                |
|__----_______----___________________________________________________|
                                                                      
.CE

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration"

.SH "BIBLIOGRAPHY"
.iB "MPC7400 User's Manual",
.iB "MPC750 RISC Microprocessor User's Manual"
.iB "Motorola PowerPC Microprocessor Family: The Programming Environments,"
.iB "Motorola Computer Group Online Documentation, http://library.mcg.mot.com/mcg/boards",
.iB "Intel 82559ER Fast Ethernet PCI Bus Controller with Integrated PHY,"
.iB "SGS-Thomson M48T37v 32KB RTC/NVRAM Data Sheet,"
.iB "Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1,"
.iB "PCI to PCI Bridge Architecture Specification 2.0,"
.iB "IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC),"