target.nr

LoPEC Early Access VxWorks BSP

lf3 lf3
l l .
Vector/IRQ#	Assigned to
_
00	Timer 1/Counter 0 (*)
01	Legacy Keyboard IRQ from USB controller (*)
02	[Cascade interrupt from PIC2]
03	Reserved
04	Reserved
05	Reserved
06	Reserved
07	Legacy Mouse IRQ from USB controller (*)
08	Reserved
09	Reserved
10	Reserved
11	Reserved
12	Legacy Mouse IRQ from USB controller (*)
13	ISA DMA complete  (*)
14	Primary IDE interrupt 
15	Secondary IDE interrupt 
.TE

.CS
(*) - Not supported for this BSP.
.CE



The Embedded Programmable Interrupt Controller (EPIC) sets system interrupt
priorities and serves as controller of all external interrupts.  Each
of its 16 interrupt control registers can be programmed with a relative
priority from 15, the highest, to 0, the lowest.  A priority of zero
effectively disables the interrupt.  All of the 16 control registers have
been hard-wired to a particular interrupt source.  The EPIC interrupt
controller will operate in the serial interrupt mode.

The external interrupt vector numbers and priority assignments are:


.TS C
center;
lf3 lf3 lf3 lf3
l l l l .
.ne 14
.sp .5
EPIC IRQ#	Vector#	EPIC Priority	Interrupt Source
_
0x0	0x10	0x3	PIB (EIDE)
0x1	0x11	0x14	i82559 Ethernet Controller
0x2	0x12	0x0	Unused
0x3	0x13	0x0	Unused
0x4	0x14	0x8	X-port COM 2
0x5	0x15	0x8	X-port COM 3
0x6	0x16	0x3	SCSI controller
0x7	0x17	0x13	PCI Expansion Interrupt 1 (a)
0x8	0x18	0x13	PCI Expansion Interrupt 2 (b)
0x9	0x19	0x13	PCI Expansion Interrupt 3 (c)
0xa	0x1a	0x13	PCI Expansion Interrupt 4 (d)
0xb	0x1b	0x3	USB Host Controller (*)
0xc	0x1c	0x0	Peripheral Parallel Controller (*)
0xd	0x1d	0x8	X-port COM 1
0xe	0x1e	0x4	Abort Switch (*)
0xf	0x1f	0x5	RTC/IRQ 
.TE

.CS
(*) - Not supported in this BSP
(a) - PMC slot 1 INTA or PMC slot 2 INTD or PCI slot 3 INTC
(b) - PMC slot 1 INTB or PMC slot 2 INTA or PCI slot 3 INTD
(c) - PMC slot 1 INTC or PMC slot 2 INTB or PCI slot 3 INTA
(d) - PMC slot 1 INTD or PMC slot 2 INTC or PCI slot 3 INTB
.CE

For further details, refer to the appropriate board reference guide.

.SS "PCI Support"
The 32-bit PCI bus is fully supported under the 
.I PCI Local Bus Specification, Revision 2.1. 
The 64-bit extensions are not supported.  All configuration space accesses 
are made with BDF (bus number, device number, function number) format calls 
in the pciConfigLib module. 
To simplify the addition of PCI-based add-in cards, the BSP provides a PCI
auto-configuration library. The BSP will automatically locate and configure 
installed PCI devices.  This configuration, performed during initialization
immediately after power-up programs PCI memory BARs, interrupt lines, and
other appropriate PCI configuration information for all PCI devices.
The starting addresses and extents of PCI spaces are documented in 
sysBusPci.c.

.SS "System Memory Error Detection and Correction"
The BSP provides support for all three types of memory error detection
and correction: 0 (no parity), 1 (normal and RMW parity as well as ECC),
and 2 (RMW parity and ECC).  When type 0 memory is detected, the MPC107
PCI Bridge/Memory Controller is configured for no parity or ECC, regardless 
of the setting of INCLUDE_ECC.  If type 1 or 2 memory is detected and 
INCLUDE_ECC is not defined, the memory controller is configured for RMW 
parity.  If type 1 or 2 memory is detected and INCLUDE_ECC is defined, 
the memory controller is configured for ECC.

When ECC is enabled, single-bit errors are detected and corrected but
neither single-bit nor multiple-bit errors are reported.  The MPC107 
reports single-bit and multiple-bit errors by asserting the machine
check signal to the processor.  In order to enable ECC you must 
replace the "#undef INCLUDE_ECC", in config.h, with "#define INCLUDE_ECC", 
and rebuild the bootrom and kernel.

.SS "Serial Configuration"
The three serial ports on the LoPEC board family are implemented as SCC
16550 UARTS.  The RJ-45 jack is placed as an edge connector on the board
and is configured as a DTE connection.  It serves as the COM1 interface.
The COM2/3 interfaces are implemented as two ten-pin headers labeled
J29 and J30 (see diagram at the end of this document).

By default, the serial port is configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software
handshake.  Hardware handshake using RTS/CTS is a supported option.

.SS "SCSI Configuration"
SCSI is supported on the LoPEC through the Symbios/LSI Logic SYM53C895A PCI
to Ultra2 SCSI controller.  To enable SCSI you must replace the
"#undef INCLUDE_SCSI", in config.h, with "#define INCLUDE_SCSI", and rebuild
the bootrom and kernel.

The following defines are used to configure SCSI support, and can also be
found in config.h:

.TS C
expand;
cf2 s
lf3 lf3
l l .
Define	Description
_
`INCLUDE_SCSI_BOOT'	Enables booting from a SCSI device.  It is defined by default.	
`INCLUDE_DOSFS'	Enables DOS file system support.  It is defined by default.	
`SCSI_AUTO_CONFIG'	Enables an automatic scan of the SCSI bus at startup.  It is undefined by default.	
`SYS_SCSI_CONFIG'	Enables you to declare a SCSI peripheral configuration, and is meant as a substitute for SCSI_AUTO_CONFIG.  You must also edit sysScsiConfig in sysScsi.c, so that it reflects the actual configuration of your SCSI bus.  It is undefined by default.	
.TE

.IP "1)"
To configure unformatted SCSI hard drives you use the following commands:

If SCSI_AUTO_CONFIG is not defined in config.h, substitute <ID> and <LUN> with 
the SCSI ID and logical unit number for your SCSI drive, and execute the 
following to format and mount the scsi drive:
.CS
        pPhysDev0 = scsiPhysDevCreate(pSysScsiCtrl,<ID>,<LUN>,0,-1,0,0,0)
        pBlkDev0 = scsiBlkDevCreate(pPhysDev0, 0, 0)
        pDosVolDesc = dosFsMkfs ("/sd0", pBlkDev0)
.CE
If SCSI_AUTO_CONFIG is defined in config.h, execute the following at the
vxWorks kernel prompt:
.CS
        Type "scsiShow" at the kernel prompt, which will display the following:

     ID LUN  VendorID  ProductID       Rev. Type   Blocks  BlkSize pScsiPhysDev
     --------------------------------------------------------------------------
     0  0    SEAGATE   ST11200N ST31230 0660  0    2069860  512     0x01fcb4dc
     1  0    SEAGATE   ST12400N ST32171 0460  0    4194158  512     0x01fc9a50

     Next, using the pScsiPhysDev value from the resulting table, execute the
     following commands:

        pBlkDev0 = scsiBlkDevCreate(pScsiPhysDev, 0, 0)
        pDosVolDesc = dosFsMkfs("/sd0",pBlkDev0)
.CE
.IP "2)"
To configure formatted SCSI hard drives you use the following commands:
.CS
        Type "scsiShow" at the kernel prompt, which will display the following:

     ID LUN  VendorID  ProductID       Rev. Type   Blocks  BlkSize pScsiPhysDev
     --------------------------------------------------------------------------
     0  0    SEAGATE   ST11200N ST31230 0660  0    2069860  512     0x01fcb4dc
     1  0    SEAGATE   ST12400N ST32171 0460  0    4194158  512     0x01fc9a50

     Next, using the pScsiPhysDev value from the resulting table, execute the
     following commands:

        pBlkDev0 = scsiBlkDevCreate(pScsiPhysDev, 0, 0)
        pDosVolDesc = dosFsDevInit("/sd0",pBlkDev0, -1)
.CE

.SS "Network Configuration"
All boards have one Ethernet port which is 10baseT and 100baseTX compatible.
The port is implemented as an RJ45 edge connector.

The Ethernet driver automatically senses and configures the port as 10baseT or
100baseTX.

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the i82559 chip.  If the address is not found in
serial ROM, the driver attempts to read it from NVRAM.

.SS "Compact Flash Configuration"
Compact Flash is supported on the LoPEC as IDE controller 1, device 0.  Once
you have a Compact Flash device installed, you will need to configure it by
performing the following:
.IP "1)"
In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".
.IP "2)"
Make sure that the ATA_DEV2_STATE line reads:

.CS
	#define ATA_DEV2_STATE DEV_PRESENT
.CE
.IP "3)"
Rebuild the kernel.  After booting, the Compact Flash device can be
configured with the following command:

	If a dosFs file system has never been set up on the device:
.CS
	pDisk = ataDevCreate(1,0,0,0)
	pAtaVol = dosFsMkfs("/ata2",pDisk)
.CE
			OR

	If a dosFs file system has previously been set up on the device:
.CS
	usrAtaConfig(1,0,"/ata2")
.CE

.SS "EIDE Disk Configuration"
ATA-33 3.5 inch disk EIDE is supported on the LoPEC as IDE controller 0,
device 0 for the master device, and device 1 for the slave device.  2.5
inch disk EIDE is supported as IDE controller 0, device 0 for the master
device, and device 1 for the slave device.  The 3.5 inch and 2.5 inch 
EIDE header cannot be populated at the same time.  Once you have an EIDE 
disk installed you will need to configure it by performing the following:
.IP "1)"
In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".
.IP "2)"
Make sure that the appropriate ATA_DEVn_STATE is set to DEV_PRESENT:

.CS
	#define ATA_DEV0_STATE DEV_PRESENT   /* 3.5/2.5 inch master device */
	#define ATA_DEV1_STATE DEV_PRESENT   /* 3.5/2.5 inch slave device  */
.CE
.IP "3)"
Rebuild the kernel.  After booting, the EIDE disks can be configured with
the following commands:
	
	If a dosFs file system has never been set up on the device:
.CS
	pDisk = ataDevCreate(<controller#>,<device#>,<#ofblocks>,<blockoffset>)
	pAtaVol = dosFsMkfs("<mountpoint>",pDisk)
.CE
			OR

	If a dosFs file system has previously been set up on the device:
.CS
	usrAtaConfig(<controller#>,<device#>,"/ata<#>")
.CE

For example, to set up a dosFs file system on a 3.5 inch master device you 
would use the following commands:

.CS
	pDisk = ataDevCreate(0,0,0,0)
	pAtaVol = dosFsMkfs("/ata0",pDisk)
.CE

.SS "Failsafe Timer"

Support for a failsafe ( ie. watchdog ) timer is provided.  The failsafe
timer is implemented with the STMicroelectronics M48T37Y Timekeeper SRAM.
This support is not part of the standard VxWorks watchdog library, wdLib.  
Failsafe timer expiration can be reported via a maskable interrupt or
via a board reset event.  The timeout lengths range from 0 (disable) to
31 seconds.

Failsafe timer support can be included in the BSP by defining
INCLUDE_FAILSAFE in config.h.  This support by default is excluded.  There
is only one failsafe timer on the board, so only one failsafe timer can
be established at any given time.

The failsafe timer is disabled at power-up and after a reset.  The
failsafe timer support routines are defined in sysFailsafe.c.

In order to use the failsafe timer, the user will need to first call
sysFailsafeSet().  The routine takes as parameters the number of
seconds until expiration and whether or not to generate a board reset
upon expiration.  If reset is set to FALSE, an interrupt occurs, if reset
is set to TRUE, a board reset occurs.  Passing a value of 0 for seconds
will disable the failsafe timer.  Once the timer has been set, subsequent 
calls to sysFailsafeSet() will extend the timer for the specified number 
of seconds.  

A call to sysFailsafeCausedReset() will determine whether 
the failsafe timer caused the last board reset.  This information will
be lost if a call to sysAlarmSet() is made prior to calling
sysFailsafeCausedReset(). 

A call to sysFailsafeCancel() will disable the failsafe timer.  The
current failsafe timer settings can be retrieved with a call to
sysFailsafeGet().  The current failsafe timer settings can be displayed
with a call to sysFailsafeShow(), this displays the current settings
not the number of seconds until timer expiration.  The routine
sysFailsafeIntr() is the failsafe timer interrupt handler.  In order to
define your own interrupt handler, simply edit this routine.

.SS "Real-Time Clock and Alarm Clock"

Support for a real-time clock and an alarm clock are provided.  The
real-time and alarm clocks are implemented with the STMicroelectronics
M48T37Y Timekeeper SRAM.