target.nr

LoPEC Early Access VxWorks BSP

'\" t
.so wrs.an
.\" lopec/target.nr - Motorola LoPEC target-specific documentation
.\"
.\" Copyright 2001 Wind River Systems, Inc.
.\" Copyright 2000-2001 Motorola, Inc. All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01k,23apr01,cak  added unbuffered DIMMS on MPC7410 to "Known Problems"
.\" 01j,17apr01,scb  general cleanup.
.\" 01i,03apr01,cak  modified to include ECC and remove alpha release references
.\" 01h,05mar01,cak  modified to include RTC, alarm clock, failsafe timer
.\" 01g,06feb01,cak  modified to include SCSI support instructions
.\" 01f,22jan01,scb  updated memory maps for MPC107 memory map B.
.\" 01e,22jan01,djs  removed the words about SPD not working.
.\" 01d,11jan01,cak  edited IDE support instructions for 2.5 inch header
.\" 01c,04jan01,cak  modified to include ATA/IDE support instructions
.\" 01b,21dec00,scb  incorporated code review comments for alpha version.
.\" 01a,19dec00,scb  created (from mv2100/target.nr ver 01j.)
.\"
.\"
.TH "LoPEC" T "Motorola" "Rev: 19 Dec 2000" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola LoPEC - BSP"

.SH "INTRODUCTION"
This manual entry covers the BSP for VxWorks running on the LoPEC board.  
It provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board
runs in the factory configuration by using vendor-supplied ROMs and
DIP switch settings and checking the serial connection.  This BSP is 
compatible with Wind River's Tornado 2 development environment.

The LoPEC board is a single-board computer based on the PowerPC MPC750 or 
MPC7410 microprocessor and using the MPC107 PCI bridge/memory controller.

.SS "Boot ROMS"
The LoPEC boards have two sets of flash EEPROM (FLASH).  Bank 0
consists of two 32-pin PLCC sockets which can be populated with up to
1024KB of FLASH memory.  Bank 0 resides at address 0xFFF00000 and is
restricted to 8 bits in width.  This memory contains Motorola's
PPC5-Bug.  Bank 1 is populated with four 512Kx16 FLASH devices to
obtain 4MB of 64-bit wide expansion FLASH memory or four 1Mx16 FLASH
devices to obtain 8MB of 64-bit wide FLASH memory.  The expansion
FLASH memory starts at address 0xFF000000 and is soldered onto
the board.  The VxWorks bootrom image can be programmed ("pflash'ed")
into the soldered Bank 1.  See \f2Hardware Details: ROM Considerations\f1 for
information about loading and writing the boot kernel image to the
soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following DIP switch is relevant to VxWorks configuration:

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .
.ne 28
.sp .5
Switch	Function	Description
_
S1[0]	ROM Selection	T{
This switch is located on the bank of 8 DIP switches and occupies the
position closest to the edge of the board.  To run from socketed
flash-ROM the switch must be pushed toward the processor (refer
to diagram at the end of this document).  To run from soldered
flash-ROM the switch must be pushed away from the processor.  Normally
PPC5-Bug will reside in the socketed flash-ROM and the VxWorks bootrom
image will reside in soldered flash-ROM.  See "ROM considerations" for
a complete description of this.
T}
.TE

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the LoPEC board are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 7
.sp .5
Feature	Description
_
Processor	T{
MPC750 and MPC7410; 66.67 and 100 MHz bus clock
T}
FLASH	T{
1MB socketed (8-bit wide);
4 or 8MB expansion (4x16-bit wide)
T}
Memory	T{
32MB to 1GB ECC PC100 Synchronous DRAM (SDRAM);
CHRP memory model (MPC107 Memory Map B);
L1 and L2 cache
T}
NVRAM	T{
32KB (MK48T37)
T}
RTC, Alarm Clock, and Failsafe Timer	T{
MK48T37
T}
Peripherals	T{
Three 16550-compatible async serial ports;
Intel 82559 10/100Base-TX Ethernet interface;
ATA-33 3.5 inch Disk EIDE Port;
Type 2 IDE Compact Flash Port or 2.5 inch Disk EIDE Port;
Ultra2 SCSI - SYM53C895A;
On-board fail LED
T}
PCI Interface	T{
One 32-bit PCI slot.
Two PMC sites, signal wide, 33MHz, 32 bit.
T}
.TE

.SS "Unsupported Features"
The following features of the LoPEC board are not supported: 

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	
_
PrEP Memory Model (MPC107 Memory Map A)
Parallel port interface	
USB interface	
Driver for programming flash banks
True Flash File System	
Abort switch
MPC107 DMA
MPC107 Power Management Facilities
MPC107 I20 Messaging
MPC107 EPIC timers 1-3
.TE

.SS "Feature Interactions"
None known.

.SH "HARDWARE DETAILS"
This section details device drivers and board hardware elements.

.SS "Devices"
The device drivers and libraries included with this BSP are:

.TS C
expand;
cf2 s
lf3 lf3
l l .
Driver name	Description
_
`i8250Sio'	Intel 8250 (or 16550 compatible) UART driver (serial port)
`ppcDecTimer'	PowerPC decrementer timer driver (system clock)
`i82559DrvEnd.obj'	10baseT/100baseTX Intel i82559 ethernet driver
`byteNvRam'	byte-oriented generic non-volatile RAM driver
`mpc107Epic'	Motorola MPC107 EPIC interrupt controller driver
`mpc107AuxClk'	Motorola MPC107 auxiliary clock library
`sysI2cMpc107'	Motorola MPC107 I2C serial EEPROM driver
`sysIbc'	PIB interrupt controller driver (Winbond W83c554)
`pciConfigLib'	PCI configuration library
`sysI2cDrv'	MPC107 I2C interface driver
`sysMotVpd'	Vital Product Data support
`sysMotVpdUtil'	Vital Product Data Utility routines
`ataDrv'	ATA/IDE (LOCAL and PCMCIA) disk device driver
`sym895Lib.obj'	Symbios SYM53C895A PCI to Ultra2 SCSI Controller driver
`m48t37'	STMicroelectronics M48T37 Timekeeper SRAM device driver	
`sysRtc'	Real-Time Clock and Alarm Clock support routines
`sysFailsafe'	Failsafe (watchdog) Timer support routines
.TE

.SS "NETIF support"
This BSP supports the END (Enhanced Network Driver) as the only
network interface for Tornado 2.

.SS "Memory Maps"
On-board RAM for these boards always appears at address 0x0 locally.

Dynamic memory sizing is supported in this BSP release.  
It is controlled by the LOCAL_MEM_AUTOSIZE define in config.h. 

The LoPEC supports one memory mapping, the CHRP memory map (MPC107
Memory Map B), which is described in the next section.  

.SS "CHRP Address Map"
The following tables describe the CHRP address mappings, also referred
to as MPC107 "Memory Map B".  "Memory Map B" is the only memory map
supported by this BSP.  Most of the
address maps are fixed by hardware and the base addresses cannot be modified
by the user.
Note that the BSP does not make available all of the PCI space
documented below.  Instead, an adjustable set of #define's in lopec.h
and config.h specify how much space in the PCI memory map is actually
useable.  See sysBusPci.c for a memory map of what is actually
available.

.TS E
expand;
lf3 lf3 lf3
lf3 lf3 lf3
l l l .
.ne 6
Table I.    CHRP Map From CPU Point of View.
.sp .5
Processor Address	Size	Access to
_
0x00000000	LOCAL_MEM_SIZE (32MB min)	DRAM
LOCAL_MEM_SIZE	(0x40000000 - LOCAL_MEM_SIZE)	Unused DRAM space
0x40000000	1GB	Reserved
0x80000000	2GB-32MB (0x7e000000)	PCI Memory space
0xFE000000	64KB	PCI 16-bit I/O (ISA) space (*1)
0xFE010000	8MB-64KB (0x007f0000)	Reserved (*1)
0xFE800000	4MB	PCI 32-bit I/O space (*1)
0xFEC00000	2MB	PCI Configuration Addr Reg.
0xFEE00000	1MB	PCI Configuration Data Reg.
0xFEF00000	1MB	PCI interrupt Ack.
0xFF000000	8MB	64 bit soldered FLASH/ROM
0xFFF00000	1MB	8 bit socketed FLASH/ROM
.TE

.CS
(*1) - Maps to table III (PCI I/O Space Access)
.CE


.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
Table II. PCI Memory Space Access
.sp .5
PCI Address	Size	Access to
_
0x00000000	1GB (max)	DRAM space
0x40000000	1GB (fixed)	Reserved (not addressable by processor)
0x80000000	2GB-32MB (0x7e000000)	PCI MEM space
0xFE000000	32MB	Reserved (not addressable by processor)
.TE


.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
Table III. PCI I/O Space Access
.sp .5
I/O Bus Address	Size	Access to
_
0x00000000	64KB	16-bit I/O (ISA) space
0x00010000	8MB-64KB (0x007f0000)	Reserved
0x00800000	4MB	32-bit I/O space
0x00C00000	4GB-12MB	Reserved (Not addressable by processor)
.TE

.SS "Shared Memory"
Shared memory is a concept that works in a common backplane configuration
and is not supported on this board.  

.SS "Interrupts"
The system interrupt vector table has 256 entries.  Vectors for the various
devices on the buses are assigned hierarchically as follows:

.TS C
expand;
cf2 s
lf3 lf3
l l .
Vector#	Assigned to
_
0x00 - 0x0f	ISA interrupts
0x10 - 0x1f	MPC107 Epic serial interrupts
0x20 - 0x23	MPC107 Epic timer interrupts (*)
0x24 - 0x26	MPC107 Epic internal interrupts (*)
0x27 - 0x47	MPC107 Message Unit Doorbell interrupts (*)
0x48 - 0xff	[User defined]
.TE

.CS
(*) - Not supported in this BSP
.CE


The specific ISA vector number assignments are:

.TS C
expand;
cf2 s