dec21x40end.h

LoPEC Early Access VxWorks BSP

/* CSR9 Ethernet Address ROM Register */

#define	CSR9_21140_MDI	0x00080000	/* MII mgmt data in */
#define	CSR9_21140_MII	0x00040000	/* MII mgmt op mode */
#define	CSR9_21140_MDO	0x00020000	/* MII mgmt write data */
#define	CSR9_21140_MDC	0x00010000	/* MII mgmt clock */
#define	CSR9_21140_RD	0x00004000	/* Serial ROM Read */
#define	CSR9_21140_WR	0x00002000	/* Serial ROM Write */
#define	CSR9_21140_BR	0x00001000	/* boot rom select */
#define	CSR9_21140_SR	0x00000800	/* serial rom select */
#define	CSR9_21140_REG	0x00000400	/* external register select */

#define	CSR9_21040_DNV	0x80000000	/* Data not valid */
#define CSR9_DAT_MSK	0x000000FF	/* data mask */

#define ENET_ROM_SIZE	8		/* ethernet rom register size */

#define CSR9_MDO_SHF	17
#define CSR9_MDI_SHF	19
#define CSR9_MII_DBIT_RD(X)     (((X) & CSR9_21140_MDI) >> CSR9_MDI_SHF)
#define CSR9_MII_DBIT_WR(X)     (((X) & 0x1) << CSR9_MDO_SHF)

/* CSR10 Reserved */


/* CSR11 Full Duplex Register */

#define	CSR11_FDACV_MSK	0x0000FFFF	/* full duplex auto config mask */


/* CSR12 SIA status Register - 21040 */

#define	CSR12_21040_DA0	0x00000080	/* Diagnostic bit all One */
#define	CSR12_21040_DAZ	0x00000040	/* Diagnostic bit all zero */
#define	CSR12_21040_DSP	0x00000020	/* Diagnostic BIST status indicator */
#define	CSR12_21040_DSD	0x00000010	/* Diagnostic Self test done */
#define	CSR12_21040_APS	0x00000008	/* Auto polarity state */
#define	CSR12_21040_LKF	0x00000004	/* link fail status */
#define	CSR12_21040_NCR	0x00000002	/* network connection error */
#define	CSR12_21040_PAUI 0x00000001	/* pin AUI_TP indication */

/* CSR12 General Purpose Register - 21140 */

#define CSR12_21140_GPC	0x00000100      /* General purpose control */
#define CSR12_21140_MD	0x000000ff	/* General purpose mode/data */

/* CSR13 SIA connectivity Register */

#define CSR13_OE57	0x00008000	/* Output enable 5 6 7 */
#define CSR13_OE24	0x00004000	/* output enable 2 4 */
#define CSR13_OE13	0x00002000	/* output enable 1 3 */
#define CSR13_IE	0x00001000	/* input enable */	
#define CSR13_SEL_LED	0x00000f00	/* select LED and external driver */
#define CSR13_ASE_APLL	0x00000080	/* ase apll start enable */
#define CSR13_SIM	0x00000040	/* serial iface input multiplexer */
#define CSR13_ENI	0x00000020	/* encoder Input multiplexer */
#define CSR13_EDP_SIA	0x00000010	/* pll external input enable */
#define CSR13_AUI_TP	0x00000008	/* AUI - 10BASE-T or AUI */
#define CSR13_CAC_CSR	0x00000004	/* auto config register */
#define	CSR13_PS	0x00000002	/* pin AUI_TP select */	
#define CSR13_SRL_SIA	0x00000001	/* srl sia Reset */

/* CSR14 SIA xmit rcv Register */

#define CSR14_21143_T4	0x00040000      /* 1000Base-T4 -21143 */
#define CSR14_21143_TXF	0x00020000      /* 100Base-TX full duplex -21143 */
#define CSR14_21143_TXH	0x00010000      /* 100Base-TX half duplex -21143 */
#define CSR14_21143_TAS	0x00008000      /* 10Base-T/AUI autosensing -21143  */
#define CSR14_SPP	0x00004000	/* set polarity plus */
#define CSR14_APE	0x00002000	/* auto polarity enable */
#define CSR14_LTE	0x00001000	/* link test enable */
#define CSR14_SQE	0x00000800	/* signal quality generate enable */
#define CSR14_CLD	0x00000400	/* collision detect enable */
#define CSR14_CSQ	0x00000200	/* collision squelch enable */
#define CSR14_RSQ	0x00000100	/* receive squelch enable */
#define CSR14_21143_ANE 0x00000080      /* autonegotiation enable */
#define CSR14_21143_TH  0x00000040      /* 10Base-T half duplex enable */
#define CSR14_CPEN_NC	0x00000030	/* no compensation */
#define CSR14_CPEN_HP	0x00000020	/* high power mode */
#define CSR14_CPEN_DM	0x00000010	/* disable mode */
#define CSR14_LSE	0x00000008	/* link pulse send enable */
#define CSR14_DREN	0x00000004	/* driver enable */
#define CSR14_LBK	0x00000002	/* loopback enable */
#define CSR14_ECEN	0x00000001	/* encoder enable */

/* CSR15 SIA general register */

#define CSR15_21143_RMI	0x40000000      /* receive match interrupt */
#define CSR15_21143_GI1	0x20000000      /* general port interrupt 1 */
#define CSR15_21143_GI0	0x10000000      /* general port interrupt 0 */
#define CSR15_21143_CWE	0x08000000      /* control write enable */
#define CSR15_21143_RME	0x04000000      /* receive match enable */
#define CSR15_21143_GE1	0x02000000      /* GEP interrupt enable on  port 1 */
#define CSR15_21143_GE0	0x01000000      /* GEP interrupt enable on  port 0 */
#define CSR15_21143_LG3	0x00800000      /* LED/GEP3 select */
#define CSR15_21143_LG2	0x00400000      /* LED/GEP2 select */
#define CSR15_21143_LG1	0x00200000      /* LED/GEP1 select */
#define CSR15_21143_LG0	0x00100000      /* LED/GEP0 select */
#define CSR15_21143_RWR	0x00000020      /* receive watchdog release */
#define CSR15_21143_RWD	0x00000010      /* receive watchdog disable */
#define CSR15_21143_ABM	0x00000008      /* AUI/BNC mode */
#define CSR15_JCK	0x00000004	/* jabber clock */
#define CSR15_HUJ	0x00000002	/* host unjab */
#define CSR15_JBD	0x00000001	/* jabber disable */

#define CSR15_MD_MSK    0x000F0000      /* general purpose mode mask */
#define CSR15_MODE_10	0x00050000

#define CSR15_MD_VAL(x) (((x) << 16) & CSR15_MD_MSK)

/* receive descriptor */

/* receive descriptor 0 */

#define RDESC0_OWN		0x80000000	/* Own */
#define RDESC0_ES		0x00008000	/* Error summary */
#define RDESC0_LE		0x00004000
#define RDESC0_DT_SRF		0x00000000	/* serial rcvd frame */
#define RDESC0_DT_ILF		0x00001000	/* internal loop back frame */
#define RDESC0_DT_ELF		0x00002000	/* external loop back frame */
#define RDESC0_RF		0x00000800	/* runt frame */
#define RDESC0_MF		0x00000400	/* multicast frame */
#define RDESC0_FD		0x00000200	/* first descriptor */
#define RDESC0_LS		0x00000100	/* last descriptor */
#define RDESC0_TL		0x00000080	/* frame too long */
#define RDESC0_CS		0x00000040	/* collision seen */
#define RDESC0_FT		0x00000020	/* frame type */
#define RDESC0_RJ		0x00000010	/* receive watch dog */
#define RDESC0_DB		0x00000004	/* dribbling bit */
#define RDESC0_CE		0x00000002	/* crc error */
#define RDESC0_OF		0x00000001	/* Over flow */

#define DEC_FRAME_LEN_MSK	0x7FFF0000	/* Frame length mask */
#define DEC_FRAME_LEN_GET(x)	(((x) & DEC_FRAME_LEN_MSK) >> 16)
#define DEC_FRAME_LEN_SET(x)	(((x) << 16) & DEC_FRAME_LEN_MSK)

/* receive descriptor 1 */

#define RDESC1_RER		0x02000000	/* recv end of ring */
#define RDESC1_RCH		0x01000000	/* second address chained */

#define RDESC1_RBS2_MSK		0x003FF800	/* RBS2 buffer 2 size */
#define RDESC1_RBS1_MSK		0x000007FF	/* RBS1 buffer 1 size */

#define RDESC1_RBS1_VAL(x)	((x) & RDESC1_RBS1_MSK)	/* multiple of 4 */
#define RDESC1_RBS2_VAL(x)	(((x) << 11) & RDESC1_RBS2_MSK)	

/* transmit descriptor */

/* xmit descriptor 0 */

#define TDESC0_OWN		0x80000000	/* own */
#define TDESC0_ES		0x00008000	/* error summary */
#define TDESC0_TO		0x00004000	/* xmit jabber time out */
#define TDESC0_LO		0x00000800	/* loss of carrier */
#define TDESC0_NC		0x00000400	/* NC No carrier */
#define TDESC0_LC		0x00000200	/* late collision */	
#define TDESC0_EC		0x00000100	/* excessive collision */
#define TDESC0_HF		0x00000080	/* heart beat fail */
#define TDESC0_LF		0x00000004	/* link fail */
#define TDESC0_UF		0x00000002	/* underflow error */
#define TDESC0_DE	        0x00000001	/* deffered */

#define TDESC0_CC_MSK		0x00000078
#define	TDESC0_CC_VAL(X)	(((X) & TDESC0_CC_MSK) >> 3)    

/* xmit descriptor 1 */

#define TDESC1_IC		0x80000000	/* interrupt on completion */
#define TDESC1_LS		0x40000000	/* last segment */
#define TDESC1_FS		0x20000000	/* first segment */
#define TDESC1_FT1		0x10000000	/* filtering type */
#define TDESC1_SET		0x08000000	/* setup packet */
#define TDESC1_AC		0x04000000	/* add crc disable */
#define TDESC1_TER		0x02000000	/* xmit end of ring */
#define TDESC1_TCH		0x01000000	/* second address chained */
#define TDESC1_DPD		0x00800000	/* disabled padding */
#define TDESC1_FT0		0x00400000	/* filtering type */

#define TDESC1_TBS2_MSK		0x003FF800	/* TBS2 buffer 2 size */
#define TDESC1_TBS1_MSK		0x000007FF	/* TBS2 buffer 1 size */

#define TDESC1_TBS1_PUT(x)	((x) & TDESC1_TBS1_MSK)	/* multiple of 4 */
#define TDESC1_TBS2_PUT(x)	(((x) << 11) & TDESC1_TBS2_MSK)

#define FLTR_FRM_SIZE		0xC0		/* filter frm size 192 bytes */
#define FLTR_FRM_SIZE_ULONGS	(FLTR_FRM_SIZE / sizeof (ULONG))
#define FLTR_FRM_ADRS_NUM	0x10		/* filter frm holds 16 addrs */
#define FLTR_FRM_ADRS_SIZE	0x06		/* size of each phys addrs */
#define FLTR_FRM_DEF_ADRS	0xFFFFFFFF	/* enet broad cast address */
#define FLTR_FRM_PHY_ADRS_OFF	156             /* word - 39 */

#define DEC_CRC_POLY		0x04c11db6   /* for CRC computation */
#define DEC_FLT_INDEX(I)	((((I) & ~0x1) * 2) + ((I) & 0x1))

/* MII Defines */

#define	MII_MGMT_WR_OFF		17
#define	MII_MGMT_WR		((ULONG) 0x00020000)
#define	MII_WRITE		((ULONG) 0x00002000)
#define	MII_READ		((ULONG) 0x00044000)
#define	MII_MGMT_CLOCK		((ULONG) 0x00010000)
#define	MII_READ_FRM		((ULONG) 0x60000000)
#define MII_WRITE_FRM		((ULONG) 0x50020000)
#define	MII_PHY_CTRL_RES	((USHORT) 0x007F)
#define	MII_PHY_STAT_RES	((USHORT) 0x07C0)
#define	MII_PHY_NWAY_RES	((USHORT) 0x1C00)
#define	MII_PHY_NWAY_EXP_RES	((USHORT) 0xFFE0)
#define	MII_MGMT_DATA_IN	((ULONG) 0x00080000)
#define	MII_READ_DATA_MSK	MII_MGMT_DATA_IN

#define DEC_MAX_PHY              32      /* max number of PHY devices */
#define DEC_MAX_LINK_TOUT        6       /* max link timeout (in secs) */

#define MII_PREAMBLE            ((ULONG) 0xFFFFFFFF)
#define MII_LINK_STATUS		0x4

/* MII frame header format */

#define MII_SOF                 0x4     /* start of frame */
#define MII_RD                  0x2     /* op-code: Read */
#define MII_WR                  0x1     /* op-code: Write  */

/* MII PHY registers */

#define MII_PHY_CR              0x00    /* Control Register */
#define MII_PHY_SR              0x01    /* Status Register */
#define MII_PHY_ID0             0x02    /* Identifier Register 0 */
#define MII_PHY_ID1             0x03    /* Identifier Register 1 */
#define MII_PHY_ANA             0x04    /* Auto Negot'n Advertisement */
#define MII_PHY_ANLPA           0x05    /* Auto Negot'n Link Partner Ability */
#define MII_PHY_ANE             0x06    /* Auto Negot'n Expansion */

/* MII PHY Control Register */

#define MII_PHY_CR_RESET        0x8000  /* PHY reset  */
#define MII_PHY_CR_LOOPBACK     0x4000  /* enable loopback mode */
#define MII_PHY_CR_SPEED_LSB    0x2000  /* LSB of speed select */
#define MII_PHY_CR_AUTONEGEN    0x1000  /* Auto-negotiation process enable */
#define MII_PHY_CR_PWRDWN       0x0800  /* power down */
#define MII_PHY_CR_ISOLATE      0x0400  /* electrical isolation */
#define MII_PHY_CR_RESTARTANE   0x0200  /* restart auto-negotiation */
#define MII_PHY_CR_DUPLEX       0x0100  /* duplex mode 1 = FD */
#define MII_PHY_CR_COLLTEST     0x0080  /* collision test */
#define MII_PHY_CR_SPEED_MSB    0x0040  /* MSB of speed select */

/* MII PHY Status Register */

#define MII_PHY_SR_ANC          0x0020  /* auto-negotiation complete */
#define MII_PHY_SR_RFAULT       0x0010  /* remote fault */
#define MII_PHY_SR_ANABLE       0x0008  /* auto-negotiation capable */
#define MII_PHY_SR_LINK         0x0004  /* link status 1 = up */
#define MII_PHY_SR_JABBER       0x0002  /* jabber detect */
#define MII_PHY_SR_EXTCAP       0x0001  /* extended capabilities */

/* MII PHY Auto Negotiation Advertisement Register */

#define MII_PHY_ANA_TAF		0x03e0  /* Technology Ability Field */
#define MII_PHY_ANA_T4AM	0x0200  /* T4 Technology Ability Mask */
#define MII_PHY_ANA_TXAM	0x0180  /* TX Technology Ability Mask */
#define MII_PHY_ANA_FDAM	0x0140  /* Full Duplex Technology Ability Mask */
#define MII_PHY_ANA_HDAM	0x02a0  /* Half Duplex Technology Ability Mask */
#define MII_PHY_ANA_100M	0x0380  /* 100Mb Technology Ability Mask */
#define MII_PHY_ANA_10M		0x0060  /* 10Mb Technology Ability Mask */
#define MII_PHY_ANA_CSMA	0x0001  /* CSMA-CD Capable */

/* MII PHY Auto Negotiation Remote End Register */

#define MII_PHY_ANLPA_NP	0x8000  /* Next Page (Enable) */
#define MII_PHY_ANLPA_ACK	0x4000  /* Remote Acknowledge */
#define MII_PHY_ANLPA_RF	0x2000  /* Remote Fault */
#define MII_PHY_ANLPA_TAF	0x03e0  /* Technology Ability Field */
#define MII_PHY_ANLPA_T4AM	0x0200  /* T4 Technology Ability Mask */
#define MII_PHY_ANLPA_TXAM	0x0180  /* TX Technology Ability Mask */
#define MII_PHY_ANLPA_FDAM	0x0140  /* Full Duplex Technology Ability Mask */
#define MII_PHY_ANLPA_HDAM	0x02a0  /* Half Duplex Technology Ability Mask */
#define MII_PHY_ANLPA_100M	0x0380  /* 100Mb Technology Ability Mask */