dec21x40end.h

LoPEC Early Access VxWorks BSP

/* dec21x40End.h - DEC Ethernet LAN Controller 21x40 interface header */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 2000 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01a,02nov00,djs  created based on 01q,19aug99,dmw mv2100
*/

#ifndef __INCdec21x40Endh
#define __INCdec21x40Endh

#ifdef __cplusplus
extern "C" {
#endif

#include "end.h"
#include "netBufLib.h"

#define DECPCI_REG_OFFSET		0x08	/* quad word aligned */

/* Endian safe macros - PCISWAP, PCISWAP_SHORT, SROM_SHORT */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#   define PCISWAP(x)		LONGSWAP(x)
#   define PCISWAP_SHORT(x)	(MSB(x) | LSB(x) << 8)
#else
#   define PCISWAP(x)		(x)			
#   define PCISWAP_SHORT(x)	(x)
#endif /* _BYTE_ORDER == _BIG_ENDIAN */

#define SROM_SHORT(pX)		(*(UINT8*)(pX) | *((UINT8*)(pX)+1) << 8)

/*
 * Receive Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */
typedef struct rDesc
    {
    ULONG	rDesc0;		/* status and ownership */
    ULONG	rDesc1;		/* control & buffer count */
    ULONG	rDesc2;		/* buffer address 1 */
    ULONG	rDesc3;		/* buffer address 2 */
    } DEC_RD;

/*
 * Transmit Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */
typedef struct tDesc
    {
    ULONG	tDesc0;		/* status and ownership */
    ULONG	tDesc1;		/* control & buffer count */
    ULONG	tDesc2;		/* buffer address 1 */
    ULONG	tDesc3;		/* buffer address 2 */
    } DEC_TD;

#define MIN_RDS		5	/* 5 buffers reasonable minimum */	
#define MIN_TDS		5	/* 5 buffers reasonable minimum */
#define NUM_RDS_DEF	32	/* default number of Recv descriptors */
#define NUM_TDS_DEF	64	/* default number of Xmit descriptors */
#define NUM_LOAN	16      /* number of loaner buffers */

/* define CSRs and descriptors */

#define CSR0	0		/* csr 0 */
#define CSR1	1		/* csr 1 */
#define CSR2	2		/* csr 2 */
#define CSR3	3		/* csr 3 */
#define CSR4	4		/* csr 4 */
#define CSR5	5		/* csr 5 */
#define CSR6	6		/* csr 6 */
#define CSR7	7		/* csr 7 */
#define CSR8	8		/* csr 8 */
#define CSR9	9		/* csr 9 */
#define CSR10	10		/* csr 10 */
#define CSR11	11		/* csr 11 */
#define CSR12	12		/* csr 12 */
#define CSR13	13		/* csr 13 */
#define CSR14	14		/* csr 14 */
#define CSR15	15		/* csr 15 */

#define RDESC0	0		/* recv desc 0 */
#define RDESC1	1		/* recv desc 1 */
#define RDESC2	2		/* recv desc 2 */
#define RDESC3	3		/* recv desc 3 */

#define TDESC0	0		/* xmit desc 0 */
#define TDESC1	1		/* xmit desc 1 */
#define TDESC2	2		/* xmit desc 2 */
#define TDESC3	3		/* xmit desc 3 */
	
/* command status register read write */

#define CSR(base,x)		((ULONG)(base) + ((DECPCI_REG_OFFSET) * (x)))

#define READ_CSR(base,x)	(PCISWAP(*((ULONG *)CSR((base),(x)))))

#define WRITE_CSR(base,x,val)	(*((ULONG *)CSR((base),(x))) = PCISWAP((val)))


/* recv xmit descriptor read write */

#define DESC(base,x)		((ULONG)(base) + (4 * (x)))

#define READ_DESC(base,x)	(PCISWAP(*((ULONG *)(DESC((base),(x))))))

#define WRITE_DESC(base,x,val)	(*((ULONG *)(DESC((base),(x)))) = PCISWAP((val)))


/* Definitions for fields and bits in the DEC_DEVICE */

/* CSR0 Bus Mode Register */

#define	CSR0_21140_RML	0x00200000	/* pci read multiple - 21140 */
#define CSR0_21140_DBO	0x00100000      /* descriptor byte ordering - 21140 */
#define CSR0_TAP_NO	0x00000000	/* no xmit auto polling */
#define CSR0_TAP_200	0x00020000	/* xmit poll every 200 usecs */
#define CSR0_TAP_800	0x00040000	/* xmit poll every 800 usecs */
#define CSR0_TAP_1600	0x00060000	/* xmit poll every 1.6 millsecs */
#define	CSR0_TAP_12	0x00080000	/* xmit poll every 12.8 usecs - 21140 */
#define	CSR0_TAP_25	0x000A0000	/* xmit poll every 25.6 usecs - 21140 */
#define	CSR0_TAP_51	0x000C0000	/* xmit poll every 51.2 usecs - 21140 */
#define	CSR0_TAP_102	0x000E0000	/* xmit poll every 102.4 usecs- 21140 */
#define CSR0_DAS	0x00010000	/* Diagnostic Address Space */
#define CSR0_CAL_NO	0x00000000	/* cache address alignment not used */
#define CSR0_CAL_08	0x00004000	/* 08 longword boundary aligned */
#define CSR0_CAL_16	0x00008000	/* 16 longword boundary aligned */
#define CSR0_CAL_32	0x0000c000	/* 32 longword boundary aligned */
#define	CSR0_PBL_UL	0x00000000	/* dma burst len - unlimited */
#define	CSR0_PBL_01	0x00000100	/* dma burst len -  1 lword */
#define	CSR0_PBL_02	0x00000200	/* dma burst len -  2 lwords */
#define	CSR0_PBL_04	0x00000400	/* dma burst len -  4 lwords */
#define	CSR0_PBL_08	0x00000800	/* dma burst len -  8 lwords */
#define	CSR0_PBL_16	0x00001000	/* dma burst len - 16 lwords */
#define	CSR0_PBL_32	0x00002000	/* dma burst len - 32 lwords */
#define CSR0_BLE	0x00000080	/* Big/little endian */
#define CSR0_BAR	0x00000002	/* Bus arbitration */
#define CSR0_SWR	0x00000001	/* software reset */

#define CSR0_PBL_MSK	0x00003F00	/* Dma burst length mask */
#define CSR0_PBL_VAL(x)	(((x) << 8) & CSR0_PBL_MSK)

#define CSR0_DSL_MSK	0x0000007C	/* Descriptor skip length */
#define CSR0_DSL_VAL(x) (((x) << 2) & CSR0_DSL_MSK)

#define CSR0_TAP_MSK	0x00060000
#define CSR0_BLE_MSK	0x00000080
#define	CSR0_CAL_MSK	0x0000c000


/* CSR1 Transmit Poll Demand Register */

#define CSR1_TPD	0x00000001	/* Transmit poll demand */

/* CSR2 Recieve Poll Demand Register */

#define CSR2_RPD	0x00000001	/* Transmit poll demand */

/* CSR3 Receive List Base address Register */

#define CSR3_RDBA_MSK	0xFFFFFFFC	/* long word aligned */
#define CSR3_RDBA_VAL(x) ((x) & CSR3_RDBA_MSK)

/* CSR4 Transmit List Base address Register */

#define CSR4_TDBA_MSK	0xFFFFFFFC	/* long word aligned */
#define CSR4_TDBA_VAL(x) ((x) & CSR4_TDBA_MSK)

/* CSR5 Status register */

#define CSR5_ERR_PE	0x00000000	/* parity error */
#define CSR5_ERR_MA	0x00800000	/* Master abort */
#define CSR5_ERR_TA	0x01000000	/* target abort */

#define CSR5_TPS_ST	0x00000000	/* Stopped */
#define CSR5_TPS_RFTD	0x00100000	/* Running Fetch xmit descriptor */
#define CSR5_TPS_RWET	0x00200000	/* Running Wait for end of Xmission */
#define CSR5_TPS_RRBM	0x00300000	/* Running Read buff from memory */
#define CSR5_TPS_RSP	0x00500000	/* Running Set up packet */
#define CSR5_TPS_STFU	0x00600000	/* Suspended xmit FIFO underflow */
#define CSR5_TPS_RCTD	0x00700000	/* Running Close xmit descriptor */

#define CSR5_RPS_ST	0x00000000	/* stopped reset or stop rcv command */
#define CSR5_RPS_RFRD	0x00020000	/* Running Fetch rcv descriptor */
#define CSR5_RPS_RCEP	0x00040000	/* Running Check end of rcv packet */
#define CSR5_RPS_RWRP	0x00060000	/* Running Wait for rcv packet */
#define CSR5_RPS_SURB	0x00080000	/* Suspended - unavailable rcv buff */
#define CSR5_RPS_RCRD	0x000A0000	/* Running close rcv descriptor */
#define CSR5_RPS_RFFF	0x000C0000	/* flush frame from rcv FIFO */
#define CSR5_RPS_RQRF	0x000E0000	/* queue the rcv frame into rcv buff */

#define CSR5_NIS	0x00010000	/* normal interrupt summary */
#define CSR5_AIS	0x00008000	/* abnormal interrupt summary */
#define CSR5_SE		0x00002000	/* system error */
#define CSR5_21040_LNF	0x00001000	/* link fail - 21040 */
#define CSR5_21040_FD	0x00000800	/* Full duplex short frm rxd - 21040 */
#define	CSR5_21140_TMR	0x00000800	/* GP timer expired - 21140 */
#define CSR5_21040_AT	0x00000400	/* AUI / 10BaseT Pin - 21040 */
#define	CSR5_21140_ETI	0x00000400	/* Early Tx intrrupt - 21140 */
#define CSR5_RWT	0x00000200	/* rcv watchdog time-out */
#define CSR5_RPS	0x00000100	/* rcv process stopped */
#define CSR5_RU		0x00000080	/* rcv buffer unavailable */
#define CSR5_RI		0x00000040	/* rcv interrupt */
#define CSR5_UNF	0x00000020	/* xmit underflow */
#define CSR5_TJT	0x00000008	/* xmit jabber time-out */
#define CSR5_TU		0x00000004	/* xmit buffer unavailable */
#define CSR5_TPS	0x00000002	/* Xmit Process stopped */
#define CSR5_TI		0x00000001	/* xmit interrupt */

#define CSR5_RPS_MSK	0x000E0000	/* Rcv process state mask */
#define CSR5_TPS_MSK	0x00700000	/* Xmit process state mask */
#define CSR5_ERR_MSK	0x03800000	/* error mask */

/* CSR6 Operation Mode Register */

#define	CSR6_21140_SC	0x80000000	/* special capture effect enable */
#define	CSR6_21140_RA	0x40000000	/* receive all */
#define	CSR6_21140_MB1	0x02000000	/* must be 1 */
#define	CSR6_21140_SCR	0x01000000	/* scrambler mode */
#define	CSR6_21140_PCS	0x00800000	/* PCS function */
#define	CSR6_21140_TTM	0x00400000	/* tx threshold mode */
#define	CSR6_21140_SF	0x00200000	/* store and forward */
#define	CSR6_21140_HBD	0x00080000	/* heartbeat disable */
#define	CSR6_21140_PS	0x00040000	/* port select */
#define	CSR6_CAE	0x00020000	/* capture effect enable */
#define	CSR6_21040_BP	0x00010000	/* back pressure */
#define	CSR6_THR_072	0x00000000	/* threshold bytes 72 */
#define	CSR6_THR_096	0x00004000	/* threshold bytes 96 */
#define	CSR6_THR_128	0x00008000	/* threshold bytes 128 */
#define	CSR6_THR_160	0x0000C000	/* threshold bytes 160 */
#define	CSR6_ST		0x00002000	/* start/stop Xmit command */
#define	CSR6_FC		0x00001000	/* Force collision mode */
#define	CSR6_OM_EL	0x00000800	/* External loopback mode */
#define	CSR6_OM_IL	0x00000400	/* Internal loopback mode */
#define	CSR6_OM_NOR	0x00000000	/* normal mode */
#define	CSR6_FD		0x00000200	/* Full Duplex mode */
#define	CSR6_21040_FKD	0x00000100	/* Flaky oscillator disable */
#define	CSR6_PM		0x00000080	/* Pass all multicast */
#define	CSR6_PR		0x00000040	/* promiscuous mode */
#define	CSR6_SB		0x00000020	/* Start/Stop Back off counter */
#define	CSR6_IF		0x00000010	/* inverse filtering [RO] */
#define	CSR6_PB		0x00000008	/* pass bad frames */
#define	CSR6_HO		0x00000004	/* hash only filter mode [RO] */
#define	CSR6_SR		0x00000002	/* start/stop receive command */
#define	CSR6_HP		0x00000001	/* hash/perfect filter mode [RO] */

/* CSR7 Interrupt Mask register */

#define	CSR7_NIM	0x00010000	/* normal interrupt mask */
#define	CSR7_AIM	0x00008000	/* abnormal interrupt mask */
#define	CSR7_SEM	0x00002000	/* system error mask */
#define	CSR7_21040_LFM	0x00001000	/* link fail mask */
#define	CSR7_21040_FDM	0x00000800	/* full duplex mask */
#define	CSR7_21140_TMR	0x00000800	/* gp timer mask */
#define	CSR7_21040_ATM	0x00000400	/* aui/tp switch mask */
#define	CSR7_21140_ETM	0x00000400	/* early trasmit mask */
#define	CSR7_RWM	0x00000200	/* rcv watchdog time-out mask */
#define	CSR7_RSM	0x00000100	/* rcv stopped mask */
#define	CSR7_RUM	0x00000080	/* rcv buff unavailable mask */
#define	CSR7_RIM	0x00000040	/* rcv  interrupt mask */
#define	CSR7_UNM	0x00000020	/* underflow interrupt mask */ 
#define	CSR7_TJM	0x00000008	/* xmit jabber timer out mask */ 
#define	CSR7_TUM	0x00000004	/* xmit buff unavailable mask */
#define	CSR7_TSM	0x00000002	/* xmission stopped mask */
#define	CSR7_TIM	0x00000001	/* xmit interrupt mask */


/* CSR8 Missing Frame Counter */

#define	CSR8_21140_OFO		0x10000000   /* overflow counter overflow */
#define	CSR8_21140_OFC_MSK	0x0FFE0000   /* overflow counter */
#define	CSR8_MFO		0x00010000   /* missed frame overflow */
#define CSR8_MFC_MSK		0x0000FFFF   /* Missed frame counter mask */