sdramspd.h

LoPEC Early Access VxWorks BSP

/* sdramSpd.h - SDRAM Serial Presence Detect definitions file */

/* Copyright 2000-2001 Wind River Systems, Inc. */
/* Copyright 1998-2001 Motorola, Inc. */

/*
modification history
--------------------
01d,27mar01,cak  corrected attribute register bit mask
01c,12jan01,djs  changes and cleanup related to SPD
01b,13dec00,djs  Cleanup/rename macros
01a,02nov00,djs  created basedon 01b,26mar99,dmw mv2100
*/

/*
This file contains the field definitions for the SDRAM Serial Presence Detect
(SPD) EEPROMs.
*/

#ifndef	INCsdramSpdh
#define	INCsdramSpdh

#ifdef __cplusplus
extern "C" {
#endif

#define MPC107_SPD_SIZE		31	/* Number of useful SPD data */
#define SPD_SIZE		MPC107_SPD_SIZE
	
#define SPD_NUM_BYTES_INDEX	 0	/* Number of Bytes Utilized index */
#define SPD_DEVICE_SIZE_INDEX	 1	/* Number of Device Bytes index */
#define SPD_MEMORY_TYPE_INDEX	 2	/* Memory Type index */
#define SPD_ROW_ADDR_INDEX	 3	/* Number of Row Addresses index */
#define SPD_COL_ADDR_INDEX	 4	/* Number of Column Addresses index */
#define SPD_NUM_DIMMBANKS_INDEX  5      /* Number of DIMM Banks index */
#define SPD_TCYC_INDEX		 9	/* SDRAM Cycle Time index */
#define SPD_DIMM_TYPE_INDEX     11      /* DIMM Configuration Type index */
#define SPD_REFRESH_RATE_INDEX	12	/* Refresh Rate/Type */
#define SPD_DEV_WIDTH_INDEX	13      /* Primary SDRAM Device Width index */ 
#define SPD_ECC_WIDTH_INDEX	14	/* Error Checking Device Width index */
#define SPD_DEV_BANKS_INDEX	17      /* Number of Device Banks index */
#define SPD_CL_INDEX		18      /* CAS latency byte index */
#define SPD_CS_LATENCY_INDEX	19	/* CS Latency index */
#define SPD_WE_LATENCY_INDEX	20	/* WE Latency index */
#define SPD_ATTRIBUTES_INDEX    21      /* SDRAM attributes index */
#define SPD_TCYC_RCL_INDEX	23	/* CAS latency @ X-1 index */
#define SPD_TCYC_RCL2_INDEX     25      /* CAS latency @ X-2 index */
#define SPD_TRP_INDEX		27      /* Row Precharge Time index */
#define SPD_TRRD_INDEX		28      /* Min Row active to Row active */
#define SPD_TRCD_INDEX 		29      /* RAS to CAS delay index */
#define SPD_TRAS_INDEX		30      /* RAS pulse width index */
#define SPD_CHECKSUM_INDEX	63	/* Checksum for bytes 0-62 index */

#define SPD_CONF_ERR_NONE	0	/* no error detection/correction */
#define SPD_CONF_ERR_PARITY	1	/* parity error detection/correction */
#define SPD_CONF_ERR_ECC	2	/* ECC error detection/correction */

#define SPD_REF_SELF_REFRESH	0x80	/* Self Refresh flag */
#define SPD_REF_NORMAL_15	0	/* Refresh Rate Normal (15.625us) */
#define SPD_REF_REDUCED_DIV4	1	/* Refresh Rate Reduced .25x (3.9us) */
#define SPD_REF_REDUCED_DIV2	2	/* Refresh Rate Reduced .5x (7.8us) */
#define SPD_REF_EXTENDED_2X	3	/* Refresh Rate Extended 2x (31.3us) */
#define SPD_REF_EXTENDED_4X	4	/* Refresh Rate Extended 4x (62.5us) */
#define SPD_REF_EXTENDED_8X	5	/* Refresh Rate Extended 8x (125us) */

#define SPD_TYPE_RESERVED	0	/* Reserved memory type (technology) */
#define SPD_TYPE_FPM_DRAM	1	/* Standard FPM DRAM memory type */
#define SPD_TYPE_EDO		2	/* EDO DRAM memory type */
#define SPD_TYPE_PIELINED	3	/* Pipelined nibble memory type */
#define SPD_TYPE_SDRAM		4	/* SDRAM memory type */

#define SPD_REFRESH_TYPE_MASK    0x80   /* Refresh Type bit field */
#define SPD_REFRESH_RATE_MASK    0x7F   /* Refresh Rate bit fields */
#define SPD_ATTR_REGISTERED_MASK 1<<1   /* Attribute register bit mask */

#ifdef __cplusplus
}
#endif

#endif	/* INCsdramSpdh */