📄 at91rm9200.h
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#ifndef __AT91RM9200_H
#define __AT91RM9200_H
/**********************************************************************
******************** peripheral id for aic and pmc *******************
**********************************************************************/
#define ID_FIQ ((unsigned) 0)
#define ID_SYS ((unsigned) 1)
#define ID_PIOA ((unsigned) 2)
#define ID_PIOB ((unsigned) 3)
#define ID_PIOC ((unsigned) 4)
#define ID_PIOD ((unsigned) 5)
#define ID_US0 ((unsigned) 6)
#define ID_US1 ((unsigned) 7)
#define ID_US2 ((unsigned) 8)
#define ID_US3 ((unsigned) 9)
#define ID_MCI ((unsigned) 10)
#define ID_UDP ((unsigned) 11)
#define ID_TWI ((unsigned) 12)
#define ID_SPI ((unsigned) 13)
#define ID_SSC0 ((unsigned) 14)
#define ID_SSC1 ((unsigned) 15)
#define ID_SSC2 ((unsigned) 16)
#define ID_TC0 ((unsigned) 17)
#define ID_TC1 ((unsigned) 18)
#define ID_TC2 ((unsigned) 19)
#define ID_TC3 ((unsigned) 20)
#define ID_TC4 ((unsigned) 21)
#define ID_TC5 ((unsigned) 22)
#define ID_UHP ((unsigned) 23)
#define ID_EMAC ((unsigned) 24)
#define ID_IRQ0 ((unsigned) 25)
#define ID_IRQ1 ((unsigned) 26)
#define ID_IRQ2 ((unsigned) 27)
#define ID_IRQ3 ((unsigned) 28)
#define ID_IRQ4 ((unsigned) 29)
#define ID_IRQ5 ((unsigned) 30)
#define ID_IRQ6 ((unsigned) 31)
/**********************************************************************
******************************* pio **********************************
**********************************************************************/
#define PIOA_BASE 0xFFFFF400
#define PIOB_BASE 0xFFFFF600
#define PIOC_BASE 0xFFFFF800
#define PIOD_BASE 0xFFFFFA00
typedef struct pio_reg{
unsigned pio_per; //wo
unsigned pio_pdr; //wo
unsigned pio_psr; //ro,0x0,0x8
unsigned Reserved_1;
unsigned pio_oer; //wo
unsigned pio_odr; //wo
unsigned pio_osr; //ro,0x0,0x18
unsigned Reserved_2;
unsigned pio_ifer; //wo
unsigned pio_ifdr; //wo
unsigned pio_ifsr; //ro,0x0,0x28
unsigned Reserved_3;
unsigned pio_sodr; //wo
unsigned pio_codr; //wo
unsigned pio_odsr; //ro,0x0,0x38
unsigned pio_pdsr; //ro
unsigned pio_ier; //wo
unsigned pio_idr; //wo
unsigned pio_imr; //ro,0x0,0x48
unsigned pio_isr; //ro
unsigned pio_mder; //wo
unsigned pio_mddr; //wo
unsigned pio_mdsr; //ro,0x0,0x58
unsigned Reserved_4;
unsigned pio_pudr; //wo
unsigned pio_puer; //wo
unsigned pio_pusr; //ro,0x0,0x68
unsigned Reserved_5;
unsigned pio_asr; //wo
unsigned pio_bsr; //wo
unsigned pio_absr; //ro,0x0,0x78
unsigned Reserved_6[9];
unsigned pio_ower; //wo
unsigned pio_owdr; //wo
unsigned pio_owsr; //ro,0x0,0xa8
unsigned Reserved_7;
} pio_reg_s, *pio_reg_p;
/* pio multiplexing */
#define DRXD (0x1<<30) //dbgu
#define DTXD (0x1<<31)
//emac
#define ETXCK (0x1<<7) //pioa, asr
#define ETXEN (0x1<<8)
#define ETX01 (0x3<<9)
#define ECRS (0x1<<11)
#define ERX01 (0x3<<12)
#define ERXER (0x1<<14)
#define EMDC (0x1<<15)
#define EMDIO (0x1<<16)
#define ETX23 (0x3<<12) //piob, bsr
#define EXTER (0x1<<14)
#define ERX23 (0x3<<15)
#define ERXDV (0x1<<17)
#define ECOL (0x1<<18)
#define ERXCK (0x1<<19)
#define EF100 (0x1<<25)
#define LED1 (0x1<<20) //custom led
#define LED2 (0x1<<19)
#define LED3 (0x1<<18)
/**********************************************************************
******************************* pmc **********************************
**********************************************************************/
#define PMC_BASE 0xFFFFFC00
typedef struct pmc_reg{
unsigned pmc_scer; //wo
unsigned pmc_scdr; //wo
unsigned pmc_scsr; //ro, 0x1
unsigned Reserved_1;
unsigned pmc_pcer; //wo
unsigned pmc_pcdr; //wo
unsigned pmc_pcsr; //ro, 0x0
unsigned Reserved_2;
unsigned ckgr_mor; //rw, 0x0
unsigned ckgr_mcfr; //ro
unsigned ckgr_pllar; //rw, 0x3f00
unsigned ckgr_pllbr; //rw, 0x3f00
unsigned pmc_mckr; //rw, 0x0
unsigned Reserved_3[3];
unsigned pmc_pck[4]; //rw, 0x0
unsigned Reserved_4[4];
unsigned pmc_ier; //wo
unsigned pmc_idr; //wo
unsigned pmc_sr; //ro
unsigned pmc_imr; //ro, 0x0
} pmc_reg_s, *pmc_reg_p;
/**********************************************************************
******************************* aic **********************************
**********************************************************************/
#define AIC_BASE 0xFFFFF000
typedef struct aic_reg{
unsigned aic_smr[32]; //rw, 0x0, 0x0
unsigned aic_svr[32]; //rw, 0x0, 0x80
unsigned aic_ivr; //ro, 0x0, 0x100
unsigned aic_fvr; //ro, 0x0
unsigned aic_isr; //ro, 0x0
unsigned aic_ipr; //ro, 0x0
unsigned aic_imr; //ro, 0x0
unsigned aic_cisr; //ro, 0x0
unsigned Reserved_1[2];
unsigned aic_iecr; //wo, , 0x120
unsigned aic_idcr; //wo
unsigned aic_iccr; //wo
unsigned aic_iscr; //wo
unsigned aic_eoicr; //rw, 0x0, 0x130
unsigned aic_spu; //rw, 0x0
unsigned aic_dcr; //rw, 0x0
unsigned Reserved_2;
} aic_reg_s, *aic_reg_p;
/**********************************************************************
******************************* pdc **********************************
**********************************************************************/
typedef struct pdc_reg{
unsigned periph_rpr; //32b, r/w, 0x0
unsigned periph_rcr; //16b, r/w, 0x0
unsigned periph_tpr; //32b, r/w, 0x0
unsigned periph_tcr; //16b, r/w, 0x0
unsigned periph_rnpr; //32b, r/w, 0x0
unsigned periph_rncr; //16b, r/w, 0x0
unsigned periph_tnpr; //32b, r/w, 0x0
unsigned periph_tncr; //16b, r/w, 0x0
unsigned periph_ptcr; // wo, -
unsigned periph_ptsr; // ro, 0x0
} pdc_reg_s;
/**********************************************************************
*************************** usart, dbgu ******************************
**********************************************************************/
#define DBGU_BASE 0xfffff200
typedef struct dbgu_reg{
unsigned dbgu_cr; //0x00
unsigned dbgu_mr;
unsigned dbgu_ier;
unsigned dbgu_idr;
unsigned dbgu_imr; //0x10
unsigned dbgu_sr;
unsigned dbgu_rhr;
unsigned dbgu_thr;
unsigned dbgu_brgr; //0x20
unsigned Reserved_1[7];
unsigned dbgu_cidr; //0x40
unsigned dbgu_exid;
unsigned dbgu_fnr;
unsigned Reserved_2[45];
pdc_reg_s pdc; //0x100
} dbgu_reg_s, *dbgu_reg_p;
/* status & control bits */
#define USART_RXRDY 1<<0 //dbgu_sr...
#define USART_TXRDY 1<<1
#define USART_ENDRX 1<<3
#define USART_ENDTX 1<<4
#define USART_OVRE 1<<5
#define USART_FRAME 1<<6
#define USART_PARE 1<<7
#define USART_TXEMPTY 1<<9
#define USART_TXBUFE 1<<11
#define USART_RXBUFF 1<<12
enum uart_cr {UART_RSTRX=2,UART_RSTTX,UART_RXEN,UART_RXDIS,UART_TXEN,UART_TXDIS,UART_RSTSTA};
/**********************************************************************
******************************* emac *********************************
**********************************************************************/
#define EMAC_BASE 0xFFFBC000
typedef struct emac_reg{
unsigned eth_ctl;
unsigned eth_cfg;
unsigned eth_sr;
unsigned eth_tar;
unsigned eth_tcr;
unsigned eth_tsr;
unsigned eth_rbqp;
unsigned Reserved_0;
unsigned eth_rsr;
unsigned eth_isr;
unsigned eth_ier;
unsigned eth_idr;
unsigned eth_imr;
unsigned eth_man;
unsigned Reserved_1[2];
unsigned eth_fra;
unsigned eth_scol;
unsigned eth_mcol;
unsigned eth_ok;
unsigned eth_seqe;
unsigned eth_ale;
unsigned eth_dte;
unsigned eth_lcol;
unsigned eth_ecol;
unsigned eth_cse;
unsigned eth_tue;
unsigned eth_cde;
unsigned eth_elr;
unsigned eth_rjb;
unsigned eth_usf;
unsigned eth_sqee;
unsigned eth_drfc;
unsigned Reserved_2[3];
unsigned eth_hsh;
unsigned eth_hsl;
unsigned eth_sa1l;
unsigned eth_sa1h;
unsigned eth_sa2l;
unsigned eth_sa2h;
unsigned eth_sa3l;
unsigned eth_sa3h;
unsigned eth_sa4l;
unsigned eth_sa4h;
} emac_reg_s, *emac_reg_p;
/* eth_cfg */
#define EMAC_SPD (0x1<<0)
#define EMAC_FD (0x1<<1)
#define EMAC_BR (0x1<<2)
#define EMAC_CAF (0x1<<4)
#define EMAC_NBC (0x1<<5)
#define EMAC_MTI (0x1<<6)
#define EMAC_UNI (0x1<<7)
#define EMAC_BIG (0x1<<8)
#define EMAC_EAE (0x1<<9)
#define EMAC_CLK (0x3<<10)
#define EMAC_RTY (0x1<<12)
#define EMAC_RMII (0x1<<13)
#define EMAC_CLK_8 (0x0<<10)
#define EMAC_CLK_16 (0x1<<10)
#define EMAC_CLK_32 (0x2<<10)
#define EMAC_CLK_64 (0x3<<10)
/* eth_ctl */
#define EMAC_LB (0x1<<0)
#define EMAC_LBL (0x1<<1)
#define EMAC_RE (0x1<<2)
#define EMAC_TE (0x1<<3)
#define EMAC_MPE (0x1<<4)
#define EMAC_CSR (0x1<<5)
#define EMAC_ISR (0x1<<6)
#define EMAC_WES (0x1<<7)
#define EMAC_BP (0x1<<8)
/* eth_sr */
#define EMAC_LINK (0x1<<0)
#define EMAC_MDIO (0x1<<1)
#define EMAC_IDLE (0x1<<2)
/* eth_rsr */
#define EMAC_BNA (0x1<<0)
#define EMAC_REC (0x1<<1)
#define EMAC_OVR (0x1<<2)
/* eth_tsr */
#define EMAC_OVER (0x1<<0)
#define EMAC_COL (0x1<<1)
#define EMAC_RLE (0x1<<2)
#define EMAC_TIDLE (0x1<<3)
#define EMAC_BNQ (0x1<<4)
#define EMAC_COMP (0x1<<5)
#define EMAC_UND (0x1<<6)
/* Intel LXT971A PHY */
#define MII_STATUS1 0x1
#define MII_STATUS2 0x11
/**********************************************************************
******************************** tc **********************************
**********************************************************************/
#define TC0_BASE 0xFFFA0000
#define TC1_BASE 0xFFFA0000
#define TC2_BASE 0xFFFA0000
#define TC3_BASE 0xFFFA4000
#define TC4_BASE 0xFFFA4000
#define TC5_BASE 0xFFFA4000
typedef struct tcc_reg{
unsigned tc_ccr; //wo
unsigned tc_cmr; //rw,0x0
unsigned Reserved_1[2];
unsigned tc_cv; //ro,0x0
unsigned tc_ra; //rw,0x0
unsigned tc_rb; //rw,0x0
unsigned tc_rc; //rw,0x0
unsigned tc_sr; //ro,0x0
unsigned tc_ier; //wo
unsigned tc_idr; //wo
unsigned tc_imr; //ro,0x0
} tcc_reg;
typedef struct tc_reg{
tcc_reg tcc[3];
unsigned tc_bcr; //wo
unsigned tc_bmr; //rw,0x0
} tc_reg_s, *tc_reg_p;
enum tc_ccr {TC_CLKEN=0,TC_CLKDIS,TC_SWTRG};
enum tc_ier {TC_COVFS=0,TC_LOVRS,TC_CPAS,TC_CPBS,TC_CPCS,TC_LDRAS,TC_LDRBS,TC_ETRGS};
#define TIMER_CLOCK4 (0x3<<0)
#define TC_CPCTRG (0x1<<14)
#endif
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