sja1000.h

sja1000与51单片机的功能实现源代码

#ifndef SJA1000_H
#define SJA1000_H
#include  <absacc.h>
#define SJA_REG0			0x8000
#define SJA_REG1			0xA000
/***************************************************************************
SJA1000 - 0
***************************************************************************/
//...Control register section...
#define SJA_REG0_CR	XBYTE[SJA_REG0 + 0x00] // Control Register
#define SJA_REG0_CMD	XBYTE[SJA_REG0 + 0x01] // Command Register
#define SJA_REG0_SR	XBYTE[SJA_REG0 + 0x02] // Status register
#define SJA_REG0_IR	XBYTE[SJA_REG0 + 0x03] // Interrupt register
#define SJA_REG0_ACR	XBYTE[SJA_REG0 + 0x04] // Acceptance code register
#define SJA_REG0_AMR	XBYTE[SJA_REG0 + 0x05] // Acceptance code register
#define SJA_REG0_BTR0	XBYTE[SJA_REG0 + 0x06] // Bus timing 0
#define SJA_REG0_BTR1	XBYTE[SJA_REG0 + 0x07] // Bus timing 1
#define SJA_REG0_OCR	XBYTE[SJA_REG0 + 0x08] // Output control
#define SJA_REG0_TEST	XBYTE[SJA_REG0 + 0x09] // Test register

//...Transmit buffer section...
#define SJA_REG0_TxBuf0	XBYTE[SJA_REG0 + 0x0A] // Transmit buffer register 0
#define SJA_REG0_TxBuf1	XBYTE[SJA_REG0 + 0x0B] // Transmit buffer register 1
#define SJA_REG0_TxBuf2	XBYTE[SJA_REG0 + 0x0C] // Transmit buffer register 2
#define SJA_REG0_TxBuf3	XBYTE[SJA_REG0 + 0x0D] // Transmit buffer register 3
#define SJA_REG0_TxBuf4	XBYTE[SJA_REG0 + 0x0E] // Transmit buffer register 4
#define SJA_REG0_TxBuf5	XBYTE[SJA_REG0 + 0x0F] // Transmit buffer register 5
#define SJA_REG0_TxBuf6	XBYTE[SJA_REG0 + 0x10] // Transmit buffer register 6
#define SJA_REG0_TxBuf7	XBYTE[SJA_REG0 + 0x11] // Transmit buffer register 7
#define SJA_REG0_TxBuf8	XBYTE[SJA_REG0 + 0x12] // Transmit buffer register 8
#define SJA_REG0_TxBuf9	XBYTE[SJA_REG0 + 0x13] // Transmit buffer register 9

//...Receive buffer section...
#define SJA_REG0_RxBuf0	XBYTE[SJA_REG0 + 0x14] // Receive buffer register 0
#define SJA_REG0_RxBuf1	XBYTE[SJA_REG0 + 0x15] // Receive buffer register 1
#define SJA_REG0_RxBuf2	XBYTE[SJA_REG0 + 0x16] // Receive buffer register 2
#define SJA_REG0_RxBuf3	XBYTE[SJA_REG0 + 0x17] // Receive buffer register 3
#define SJA_REG0_RxBuf4	XBYTE[SJA_REG0 + 0x18] // Receive buffer register 4
#define SJA_REG0_RxBuf5	XBYTE[SJA_REG0 + 0x19] // Receive buffer register 5
#define SJA_REG0_RxBuf6	XBYTE[SJA_REG0 + 0x1A] // Receive buffer register 6
#define SJA_REG0_RxBuf7	XBYTE[SJA_REG0 + 0x1B] // Receive buffer register 7
#define SJA_REG0_RxBuf8	XBYTE[SJA_REG0 + 0x1C] // Receive buffer register 8
#define SJA_REG0_RxBuf9	XBYTE[SJA_REG0 + 0x1D] // Receive buffer register 9

#define SJA_REG0_CDR	XBYTE[SJA_REG0 + 0x1F] // Clock divider register 

/***************************************************************************
SJA1000 - 1
***************************************************************************/
//...Control register section...
#define SJA_REG1_CR	XBYTE[SJA_REG1 + 0x00] // Control Register
#define SJA_REG1_CMD	XBYTE[SJA_REG1 + 0x01] // Command Register
#define SJA_REG1_SR	XBYTE[SJA_REG1 + 0x02] // Status register
#define SJA_REG1_IR	XBYTE[SJA_REG1 + 0x03] // Interrupt register
#define SJA_REG1_ACR	XBYTE[SJA_REG1 + 0x04] // Acceptance code register
#define SJA_REG1_AMR	XBYTE[SJA_REG1 + 0x05] // Acceptance code register
#define SJA_REG1_BTR0	XBYTE[SJA_REG1 + 0x06] // Bus timing 0
#define SJA_REG1_BTR1	XBYTE[SJA_REG1 + 0x07] // Bus timing 1
#define SJA_REG1_OCR	XBYTE[SJA_REG1 + 0x08] // Output control
#define SJA_REG1_TEST	XBYTE[SJA_REG1 + 0x09] // Test register

//...Transmit buffer section...
#define SJA_REG1_TxBuf0	XBYTE[SJA_REG1 + 0x0A] // Transmit buffer register 0
#define SJA_REG1_TxBuf1	XBYTE[SJA_REG1 + 0x0B] // Transmit buffer register 1
#define SJA_REG1_TxBuf2	XBYTE[SJA_REG1 + 0x0C] // Transmit buffer register 2
#define SJA_REG1_TxBuf3	XBYTE[SJA_REG1 + 0x0D] // Transmit buffer register 3
#define SJA_REG1_TxBuf4	XBYTE[SJA_REG1 + 0x0E] // Transmit buffer register 4
#define SJA_REG1_TxBuf5	XBYTE[SJA_REG1 + 0x0F] // Transmit buffer register 5
#define SJA_REG1_TxBuf6	XBYTE[SJA_REG1 + 0x10] // Transmit buffer register 6
#define SJA_REG1_TxBuf7	XBYTE[SJA_REG1 + 0x11] // Transmit buffer register 7
#define SJA_REG1_TxBuf8	XBYTE[SJA_REG1 + 0x12] // Transmit buffer register 8
#define SJA_REG1_TxBuf9	XBYTE[SJA_REG1 + 0x13] // Transmit buffer register 9

//...Receive buffer section...
#define SJA_REG1_RxBuf0	XBYTE[SJA_REG1 + 0x14] // Receive buffer register 0
#define SJA_REG1_RxBuf1	XBYTE[SJA_REG1 + 0x15] // Receive buffer register 1
#define SJA_REG1_RxBuf2	XBYTE[SJA_REG1 + 0x16] // Receive buffer register 2
#define SJA_REG1_RxBuf3	XBYTE[SJA_REG1 + 0x17] // Receive buffer register 3
#define SJA_REG1_RxBuf4	XBYTE[SJA_REG1 + 0x18] // Receive buffer register 4
#define SJA_REG1_RxBuf5	XBYTE[SJA_REG1 + 0x19] // Receive buffer register 5
#define SJA_REG1_RxBuf6	XBYTE[SJA_REG1 + 0x1A] // Receive buffer register 6
#define SJA_REG1_RxBuf7	XBYTE[SJA_REG1 + 0x1B] // Receive buffer register 7
#define SJA_REG1_RxBuf8	XBYTE[SJA_REG1 + 0x1C] // Receive buffer register 8
#define SJA_REG1_RxBuf9	XBYTE[SJA_REG1 + 0x1D] // Receive buffer register 9

#define SJA_REG1_CDR	XBYTE[SJA_REG1 + 0x1F] // Clock divider register 
//////////////////////////////////////////////////////////////////////////////
#define MAX_CAN_RECV_LEN	180
#define MAX_MSG_LEN		50

extern unsigned char m_CanSend[];
extern unsigned char m_CanRecv[];
extern unsigned char m_can_recv_in;
extern unsigned char m_can_recv_out;
extern unsigned char m_can_recvs;

extern unsigned char xdata *m_pByte;

extern unsigned char xdata m_can_buf[];
extern unsigned char xdata m_can_msg[];

void SJA1000_init();
bit SJA1000_Send(void);
void SaveCanData(unsigned char *p_data, unsigned char len);

#endif