single.lst

一个有关EZ-USB FX2 系列CY7C68013的应用实例

 130          // DataMode NO Data   NO Data   Activate  Activate  NO Data   NO Data   NO Data            
 131          // NextData SameData  SameData  SameData  SameData  SameData  SameData  SameData           
 132          // Int Trig No Int    No Int    No Int    No Int    No Int    No Int    No Int             
 133          // IF/Wait  Wait 2    Wait 1    Wait 3    Wait 2    Wait 3    Wait 5    Wait 1             
 134          //   Term A                                                                                
 135          //   LFunc                                                                                 
 136          //   Term B                                                                                
 137          // Branch1                                                                                 
 138          // Branch0                                                                                 
 139          // Re-Exec                                                                                 
 140          // Sngl/CRC Default   Default   Default   Default   Default   Default   Default            
 141          // CONVT#       1         1         1         1         1         0         0         1    
 142          // RD#          1         1         1         1         1         1         1         1    
 143          // WR#          1         1         0         1         1         1         1         1    
 144          // CS#          1         0         0         0         1         1         1         1    
 145          // unsed        1         1         1         1         1         1         1         1    
 146          // unsed        1         1         1         1         1         1         1         1    
 147          //                     
 148          // END DO NOT EDIT     
 149                                                        
 150          // GPIF Program Code                          
 151                                                        
 152          // DO NOT EDIT ...                            
 153          #include "fx2.h"                            
 154          #include "fx2regs.h"                        
 155          #include "fx2sdly.h"     // SYNCDELAY macro 
 156          #include "gpif.h"
 157          // END DO NOT EDIT                            
 158                                                         
 159          //-------------------------------------------------------------------//                                   
             -                              
 160          // TO DO: You may add additional code below.
 161          
 162          void GpifInit( void )
 163          {
 164   1        BYTE i;
 165   1       
 166   1        // Registers which require a synchronization delay, see section 15.14
 167   1        // FIFORESET        FIFOPINPOLAR
 168   1        // INPKTEND         OUTPKTEND
 169   1        // EPxBCH:L         REVCTL
 170   1        // GPIFTCB3         GPIFTCB2
 171   1        // GPIFTCB1         GPIFTCB0
 172   1        // EPxFIFOPFH:L     EPxAUTOINLENH:L
 173   1        // EPxFIFOCFG       EPxGPIFFLGSEL
 174   1        // PINFLAGSxx       EPxFIFOIRQ
 175   1        // EPxFIFOIE        GPIFIRQ
 176   1        // GPIFIE           GPIFADRH:L
 177   1        // UDMACRCH:L       EPxGPIFTRIG
 178   1        // GPIFTRIG
C51 COMPILER V7.10   SINGLE                                                                10/04/2005 20:45:22 PAGE 4   

 179   1        
 180   1        // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
 181   1        //      ...these have been replaced by GPIFTC[B3:B0] registers
 182   1       
 183   1        // 8051 doesn't have access to waveform memories 'til
 184   1        // the part is in GPIF mode.
 185   1       
 186   1        IFCONFIG = 0x8E;
 187   1        // IFCLKSRC=1   , FIFOs executes on internal clk source
 188   1        // xMHz=1       , 48MHz internal clk rate
 189   1        // IFCLKOE=0    , Don't drive IFCLK pin signal at 48MHz
 190   1        // IFCLKPOL=0   , Don't invert IFCLK pin signal from internal clk
 191   1        // ASYNC=1      , master samples asynchronous
 192   1        // GSTATE=1     , Drive GPIF states out on PORTE[2:0], debug WF
 193   1        // IFCFG[1:0]=10, FX2 in GPIF master mode
 194   1       
 195   1        GPIFABORT = 0xFF;  // abort any waveforms pending
 196   1       
 197   1        GPIFREADYCFG = InitData[ 0 ];
 198   1        GPIFCTLCFG = InitData[ 1 ];
 199   1        GPIFIDLECS = InitData[ 2 ];
 200   1        GPIFIDLECTL = InitData[ 3 ];
 201   1        GPIFWFSELECT = InitData[ 5 ];
 202   1        GPIFREADYSTAT = InitData[ 6 ];
 203   1       
 204   1        // use dual autopointer feature... 
 205   1        AUTOPTRSETUP = 0x07;          // inc both pointers, 
 206   1                                      // ...warning: this introduces pdata hole(s)
 207   1                                      // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
 208   1        
 209   1        // source
 210   1        AUTOPTRH1 = MSB( &WaveData );
 211   1        AUTOPTRL1 = LSB( &WaveData );
 212   1        
 213   1        // destination
 214   1        AUTOPTRH2 = 0xE4;
 215   1        AUTOPTRL2 = 0x00;
 216   1       
 217   1        // transfer
 218   1        for ( i = 0x00; i < 128; i++ )
 219   1        {
 220   2          EXTAUTODAT2 = EXTAUTODAT1;
 221   2        }
 222   1       
 223   1      // Configure GPIF Address pins, output initial value,
 224   1        PORTCCFG = 0xFF;    // [7:0] as alt. func. GPIFADR[7:0]
 225   1        OEC = 0xFF;         // and as outputs
 226   1        PORTECFG |= 0x80;   // [8] as alt. func. GPIFADR[8]
 227   1        OEE |= 0x80;        // and as output
 228   1       
 229   1      // ...OR... tri-state GPIFADR[8:0] pins
 230   1      //  PORTCCFG = 0x00;  // [7:0] as port I/O
 231   1      //  OEC = 0x00;       // and as inputs
 232   1      //  PORTECFG &= 0x7F; // [8] as port I/O
 233   1      //  OEE &= 0x7F;      // and as input
 234   1       
 235   1      // GPIF address pins update when GPIFADRH/L written
 236   1        SYNCDELAY;                    // 
 237   1        GPIFADRH = 0x00;    // bits[7:1] always 0
 238   1        SYNCDELAY;                    // 
 239   1        GPIFADRL = 0x00;    // point to PERIPHERAL address 0x0000
 240   1       
C51 COMPILER V7.10   SINGLE                                                                10/04/2005 20:45:22 PAGE 5   

 241   1      // Configure GPIF FlowStates registers for Wave 0 of WaveData
 242   1        FLOWSTATE = FlowStates[ 0 ];
 243   1        FLOWLOGIC = FlowStates[ 1 ];
 244   1        FLOWEQ0CTL = FlowStates[ 2 ];
 245   1        FLOWEQ1CTL = FlowStates[ 3 ];
 246   1        FLOWHOLDOFF = FlowStates[ 4 ];
 247   1        FLOWSTB = FlowStates[ 5 ];
 248   1        FLOWSTBEDGE = FlowStates[ 6 ];
 249   1        FLOWSTBHPERIOD = FlowStates[ 7 ];
 250   1      }


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    188    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =    306    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)