📄 gpif_init.lst
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393
394 void GpifInit( void )
395 {
396 1 BYTE i;
397 1
398 1 // Registers which require a synchronization delay, see section 15.14
399 1 // FIFORESET FIFOPINPOLAR
400 1 // INPKTEND OUTPKTEND
401 1 // EPxBCH:L REVCTL
402 1 // GPIFTCB3 GPIFTCB2
403 1 // GPIFTCB1 GPIFTCB0
404 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
405 1 // EPxFIFOCFG EPxGPIFFLGSEL
406 1 // PINFLAGSxx EPxFIFOIRQ
407 1 // EPxFIFOIE GPIFIRQ
408 1 // GPIFIE GPIFADRH:L
409 1 // UDMACRCH:L EPxGPIFTRIG
410 1 // GPIFTRIG
411 1
412 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
413 1 // ...these have been replaced by GPIFTC[B3:B0] registers
414 1
415 1 // 8051 doesn't have access to waveform memories 'til
416 1 // the part is in GPIF mode.
417 1
418 1 IFCONFIG = 0x8E;
419 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
420 1 // xMHz=1 , 48MHz internal clk rate
421 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
422 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
423 1 // ASYNC=1 , master samples asynchronous
424 1 // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
425 1 // IFCFG[1:0]=10, FX2 in GPIF master mode
426 1
C51 COMPILER V7.10 GPIF_INIT 10/05/2005 08:34:24 PAGE 8
427 1 GPIFABORT = 0xFF; // abort any waveforms pending
428 1
429 1 GPIFREADYCFG = InitData[ 0 ];
430 1 GPIFCTLCFG = InitData[ 1 ];
431 1 GPIFIDLECS = InitData[ 2 ];
432 1 GPIFIDLECTL = InitData[ 3 ];
433 1 GPIFWFSELECT = InitData[ 5 ];
434 1 GPIFREADYSTAT = InitData[ 6 ];
435 1
436 1 // use dual autopointer feature...
437 1 AUTOPTRSETUP = 0x07; // inc both pointers,
438 1 // ...warning: this introduces pdata hole(s)
439 1 // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
440 1
441 1 // source
442 1 AUTOPTRH1 = MSB( &WaveData );
443 1 AUTOPTRL1 = LSB( &WaveData );
444 1
445 1 // destination
446 1 AUTOPTRH2 = 0xE4;
447 1 AUTOPTRL2 = 0x00;
448 1
449 1 // transfer
450 1 for ( i = 0x00; i < 128; i++ )
451 1 {
452 2 EXTAUTODAT2 = EXTAUTODAT1;
453 2 }
454 1
455 1 // Configure GPIF Address pins, output initial value,
456 1 PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
457 1 OEC = 0xFF; // and as outputs
458 1 PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
459 1 OEE |= 0x80; // and as output
460 1
461 1 // ...OR... tri-state GPIFADR[8:0] pins
462 1 // PORTCCFG = 0x00; // [7:0] as port I/O
463 1 // OEC = 0x00; // and as inputs
464 1 // PORTECFG &= 0x7F; // [8] as port I/O
465 1 // OEE &= 0x7F; // and as input
466 1
467 1 // GPIF address pins update when GPIFADRH/L written
468 1 SYNCDELAY; //
469 1 GPIFADRH = 0x00; // bits[7:1] always 0
470 1 SYNCDELAY; //
471 1 GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
472 1
473 1 // Configure GPIF FlowStates registers for Wave 0 of WaveData
474 1 FLOWSTATE = FlowStates[ 0 ];
475 1 FLOWLOGIC = FlowStates[ 1 ];
476 1 FLOWEQ0CTL = FlowStates[ 2 ];
477 1 FLOWEQ1CTL = FlowStates[ 3 ];
478 1 FLOWHOLDOFF = FlowStates[ 4 ];
479 1 FLOWSTB = FlowStates[ 5 ];
480 1 FLOWSTBEDGE = FlowStates[ 6 ];
481 1 FLOWSTBHPERIOD = FlowStates[ 7 ];
482 1 }
483 // TODO: You may add additional code below.
484 void OtherInit( void )
485 { // interface initialization
486 1 // ...see TD_Init( );
487 1 }
488
C51 COMPILER V7.10 GPIF_INIT 10/05/2005 08:34:24 PAGE 9
489 // Set Address GPIFADR[8:0] to PERIPHERAL
490 void Peripheral_SetAddress( WORD gaddr )
491 {
492 1 SYNCDELAY; //
493 1 GPIFADRH = gaddr >> 8;
494 1 SYNCDELAY; //
495 1 GPIFADRL = ( BYTE )gaddr; // setup GPIF address
496 1 }
497
498 // Set EP2GPIF Transaction Count
499 void Peripheral_SetEP2GPIFTC( WORD xfrcnt )
500 {
501 1 SYNCDELAY; //
502 1 EP2GPIFTCH = xfrcnt >> 8; // setup transaction count
503 1 SYNCDELAY; //
504 1 EP2GPIFTCL = ( BYTE )xfrcnt;
505 1 }
506
507 // Set EP4GPIF Transaction Count
508 void Peripheral_SetEP4GPIFTC( WORD xfrcnt )
509 {
510 1 SYNCDELAY; //
511 1 EP4GPIFTCH = xfrcnt >> 8; // setup transaction count
512 1 SYNCDELAY; //
513 1 EP4GPIFTCL = ( BYTE )xfrcnt;
514 1 }
515
516 // Set EP6GPIF Transaction Count
517
518 void Peripheral_SetEP6GPIFTC( WORD xfrcnt )
519 {
520 1 SYNCDELAY; //
521 1 EP6GPIFTCH = xfrcnt >> 8; // setup transaction count
522 1 SYNCDELAY; //
523 1 EP6GPIFTCL = ( BYTE )xfrcnt;
524 1 }
525
526
527 void Peripheral_SetEP6GPIFTCX( WORD xfrcnt )
528 {
529 1 SYNCDELAY; //
530 1 EP6GPIFTCHX = xfrcnt >> 8; // setup transaction count
531 1 SYNCDELAY; //
532 1 EP6GPIFTCLX = ( BYTE )xfrcnt;
533 1 }
534
535 // Set EP8GPIF Transaction Count
536 void Peripheral_SetEP8GPIFTC( WORD xfrcnt )
537 {
538 1 SYNCDELAY; //
539 1 EP8GPIFTCH = xfrcnt >> 8; // setup transaction count
540 1 SYNCDELAY; //
541 1 EP8GPIFTCL = ( BYTE )xfrcnt;
542 1 }
543
544 #define GPIF_FLGSELPF 0
545 #define GPIF_FLGSELEF 1
546 #define GPIF_FLGSELFF 2
547
548 // Set EP2GPIF Decision Point FIFO Flag Select (PF, EF, FF)
549 void SetEP2GPIFFLGSEL( WORD DP_FIFOFlag )
550 {
C51 COMPILER V7.10 GPIF_INIT 10/05/2005 08:34:24 PAGE 10
551 1 EP2GPIFFLGSEL = DP_FIFOFlag;
552 1 }
553
554 // Set EP4GPIF Decision Point FIFO Flag Select (PF, EF, FF)
555 void SetEP4GPIFFLGSEL( WORD DP_FIFOFlag )
556 {
557 1 EP4GPIFFLGSEL = DP_FIFOFlag;
558 1 }
559
560 // Set EP6GPIF Decision Point FIFO Flag Select (PF, EF, FF)
561 void SetEP6GPIFFLGSEL( WORD DP_FIFOFlag )
562 {
563 1 EP6GPIFFLGSEL = DP_FIFOFlag;
564 1 }
565
566 // Set EP8GPIF Decision Point FIFO Flag Select (PF, EF, FF)
567 void SetEP8GPIFFLGSEL( WORD DP_FIFOFlag )
568 {
569 1 EP8GPIFFLGSEL = DP_FIFOFlag;
570 1 }
571
572 // Set EP2GPIF Programmable Flag STOP, overrides Transaction Count
573 void SetEP2GPIFPFSTOP( void )
574 {
575 1 EP2GPIFPFSTOP = 0x01;
576 1 }
577
578 // Set EP4GPIF Programmable Flag STOP, overrides Transaction Count
579 void SetEP4GPIFPFSTOP( void )
580 {
581 1 EP4GPIFPFSTOP = 0x01;
582 1 }
583
584 // Set EP6GPIF Programmable Flag STOP, overrides Transaction Count
585 void SetEP6GPIFPFSTOP( void )
586 {
587 1 EP6GPIFPFSTOP = 0x01;
588 1 }
589
590 // Set EP8GPIF Programmable Flag STOP, overrides Transaction Count
591 void SetEP8GPIFPFSTOP( void )
592 {
593 1 EP8GPIFPFSTOP = 0x01;
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