📄 1.c
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// CTL 2 1 1 1 1 1 1 1 1
// CTL 3 1 1 1 1 1 1 1 1
// CTL 4 1 1 1 1 1 1 1 1
// CTL 5 1 1 1 1 1 1 1 1
//
// END DO NOT EDIT
// GPIF Program Code
// DO NOT EDIT ...
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
// END DO NOT EDIT
// DO NOT EDIT ...
const char xdata WaveData[128] =
{
// Wave 0
/* LenBr */ 0x20, 0x02, 0x10, 0x03, 0x01, 0x01, 0x06, 0x07,
/* Opcode*/ 0x00, 0x01, 0x00, 0x02, 0x08, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xFC, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
// Wave 1
/* LenBr */ 0x05, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x00, 0x02, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xD7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x09, 0x09, 0x12, 0x12, 0x00, 0x2D, 0x36, 0x3F,
// Wave 2
/* LenBr */ 0x02, 0x80, 0x03, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x00, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
/* Output*/ 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
// Wave 3
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x09, 0x00, 0x12, 0x12, 0x00, 0x2D, 0x36, 0x3F
};
// END DO NOT EDIT
// DO NOT EDIT ...
const char xdata FlowStates[36] =
{
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
// END DO NOT EDIT
// DO NOT EDIT ...
const char xdata InitData[7] =
{
/* Regs */ 0xA0,0x00,0x00,0xFF,0x8E,0xE4,0x01
};
// END DO NOT EDIT
// TO DO: You may add additional code below.
void GpifInit( void )
{
BYTE i;
// Registers which require a synchronization delay, see section 15.14 需要同步延时
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// 8051 doesn't have access to waveform memories 'til
// the part is in GPIF mode.
IFCONFIG = 0xCE;
// IFCLKSRC=1 , FIFOs executes on internal clk source 内部振荡源
// xMHz=1 , 48MHz internal clk rate 48M振荡频率
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz 不输出
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk 不颠倒波型
// ASYNC=1 , master samples asynchronous 异步采样
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF 波型调试在E2/E1/E0
// IFCFG[1:0]=10, FX2 in GPIF master mode gpif主控
GPIFABORT = 0xFF; // abort any waveforms pending 退出当前波型。
GPIFREADYCFG = InitData[ 0 ]; //0x80 INTRDY(B.7)=1 SAS(B.6)=0,TCXRDY5(B.5)=0
GPIFCTLCFG = InitData[ 1 ]; //0x00 TRICTL=0 6控制端都是有用的。CTL5=CTL4=CTL3=CTL2=CTL1=CTL0=0 coms输出
GPIFIDLECS = InitData[ 2 ]; //0x00 DONE=0 IDLEDRV=0 在空闲时,数据总线处于高阻状态
GPIFIDLECTL = InitData[ 3 ]; //0xFF CTL5=CTL4=CTL3=CTL2=CTL1=CTL0=1 全部输出使能,且都是高电平输出
GPIFWFSELECT = InitData[ 5 ]; //0xE4 SINGLEWR1=SINGLEWR0=SINGLERD1=FIFOWR0=1 SINGLERD0=FIFOWR1=FIFORD1=FIFORD0=0
GPIFREADYSTAT = InitData[ 6 ]; //0x01 RDY0=1,RDY5=RDY4=RDY3=RDY2=RDY1=0
// use dual autopointer feature...
AUTOPTRSETUP = 0x07; // inc both pointers, 增加所有指针
// ...warning: this introduces pdata hole(s)
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
// source
APTR1H = MSB( &WaveData );
APTR1L = LSB( &WaveData );
// destination
AUTOPTRH2 = 0xE4;
AUTOPTRL2 = 0x00;
// transfer
for ( i = 0x00; i < 128; i++ )
{
EXTAUTODAT2 = EXTAUTODAT1;
}
// Configure GPIF Address pins, output initial value, 初使化GPIF的9位地址线。
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0] 当为1则选定为GPIFADR
OEC = 0xFF; // and as outputs
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
OEE |= 0x80; // and as output
// ...OR... tri-state GPIFADR[8:0] pins 或初使化作为普通I/O口
// PORTCCFG = 0x00; // [7:0] as port I/O
// OEC = 0x00; // and as inputs
// PORTECFG &= 0x7F; // [8] as port I/O
// OEE &= 0x7F; // and as input
// GPIF address pins update when GPIFADRH/L written 当gpifadrh/l被写,gpif地址脚赋值
SYNCDELAY; //
GPIFADRH = 0x00; // bits[7:1] always 0
SYNCDELAY; //
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
//}
// Configure GPIF FlowStates registers for Wave 0 of WaveData
FLOWSTATE = FlowStates[ 0 ];
FLOWLOGIC = FlowStates[ 1 ];
FLOWEQ0CTL = FlowStates[ 2 ];
FLOWEQ1CTL = FlowStates[ 3 ];
FLOWHOLDOFF = FlowStates[ 4 ];
FLOWSTB = FlowStates[ 5 ];
FLOWSTBEDGE = FlowStates[ 6 ];
FLOWSTBHPERIOD = FlowStates[ 7 ];
}
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