📄 gpif-maxsingle.lst
字号:
179 /* Output*/ 0x3F, 0x37, 0x33, 0x37, 0x3F, 0x3E, 0x3E, 0x3F,
180 /* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
181 };
182 // END DO NOT EDIT
183
184 // DO NOT EDIT ...
185 const char xdata FlowStates[36] =
186 {
187 /* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
188 /* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
189 /* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
190 /* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
191 };
192 // END DO NOT EDIT
193
194 // DO NOT EDIT ...
195 const char xdata InitData[7] =
196 {
197 /* Regs */ 0xA0,0x00,0x00,0x3F,0x8E,0xE4,0x00
198 };
199 // END DO NOT EDIT
200
201 // TO DO: You may add additional code below.
202
203 void GpifInit( void )
204 {
205 1 BYTE i;
206 1
207 1 // Registers which require a synchronization delay, see section 15.14
208 1 // FIFORESET FIFOPINPOLAR
209 1 // INPKTEND OUTPKTEND
210 1 // EPxBCH:L REVCTL
211 1 // GPIFTCB3 GPIFTCB2
212 1 // GPIFTCB1 GPIFTCB0
213 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
214 1 // EPxFIFOCFG EPxGPIFFLGSEL
215 1 // PINFLAGSxx EPxFIFOIRQ
216 1 // EPxFIFOIE GPIFIRQ
217 1 // GPIFIE GPIFADRH:L
218 1 // UDMACRCH:L EPxGPIFTRIG
219 1 // GPIFTRIG
220 1
221 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
222 1 // ...these have been replaced by GPIFTC[B3:B0] registers
223 1
224 1 // 8051 doesn't have access to waveform memories 'til
225 1 // the part is in GPIF mode.
226 1
227 1 IFCONFIG = 0x8E;
228 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
229 1 // xMHz=1 , 48MHz internal clk rate
230 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
231 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
232 1 // ASYNC=1 , master samples asynchronous
233 1 // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
234 1 // IFCFG[1:0]=10, FX2 in GPIF master mode
235 1
236 1 GPIFABORT = 0xFF; // abort any waveforms pending
237 1
238 1 GPIFREADYCFG = InitData[ 0 ];
239 1 GPIFCTLCFG = InitData[ 1 ];
240 1 GPIFIDLECS = InitData[ 2 ];
C51 COMPILER V7.10 GPIF_MAXSINGLE 09/25/2005 16:17:29 PAGE 5
241 1 GPIFIDLECTL = InitData[ 3 ];
242 1 GPIFWFSELECT = InitData[ 5 ];
243 1 GPIFREADYSTAT = InitData[ 6 ];
244 1
245 1 // use dual autopointer feature...
246 1 AUTOPTRSETUP = 0x07; // inc both pointers,
247 1 // ...warning: this introduces pdata hole(s)
248 1 // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
249 1
250 1 // source
251 1 AUTOPTRH1 = MSB( &WaveData );
252 1 AUTOPTRL1 = LSB( &WaveData );
253 1
254 1 // destination
255 1 AUTOPTRH2 = 0xE4;
256 1 AUTOPTRL2 = 0x00;
257 1
258 1 // transfer
259 1 for ( i = 0x00; i < 128; i++ )
260 1 {
261 2 EXTAUTODAT2 = EXTAUTODAT1;
262 2 }
263 1
264 1 // Configure GPIF Address pins, output initial value,
265 1 PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
266 1 OEC = 0xFF; // and as outputs
267 1 PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
268 1 OEE |= 0x80; // and as output
269 1
270 1 // ...OR... tri-state GPIFADR[8:0] pins
271 1 // PORTCCFG = 0x00; // [7:0] as port I/O
272 1 // OEC = 0x00; // and as inputs
273 1 // PORTECFG &= 0x7F; // [8] as port I/O
274 1 // OEE &= 0x7F; // and as input
275 1
276 1 // GPIF address pins update when GPIFADRH/L written
277 1 SYNCDELAY; //
278 1 GPIFADRH = 0x00; // bits[7:1] always 0
279 1 SYNCDELAY; //
280 1 GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
281 1
282 1 // Configure GPIF FlowStates registers for Wave 0 of WaveData
283 1 FLOWSTATE = FlowStates[ 0 ];
284 1 FLOWLOGIC = FlowStates[ 1 ];
285 1 FLOWEQ0CTL = FlowStates[ 2 ];
286 1 FLOWEQ1CTL = FlowStates[ 3 ];
287 1 FLOWHOLDOFF = FlowStates[ 4 ];
288 1 FLOWSTB = FlowStates[ 5 ];
289 1 FLOWSTBEDGE = FlowStates[ 6 ];
290 1 FLOWSTBHPERIOD = FlowStates[ 7 ];
291 1 }
292
293
294
295
296
297
298
299
300
301
302
C51 COMPILER V7.10 GPIF_MAXSINGLE 09/25/2005 16:17:29 PAGE 6
303
304
305
306
307
308
309
310
311
312
313
314 #define TESTING_GPIF // NOTE: Comment this line out for frameworks based firmware
315 // See the example GPIF Tool Utility under Application
316 // Reference Material for more advanced development info
317 #ifdef TESTING_GPIF
318 // TODO: You may add additional code below.
319 void OtherInit( void )
320 { // interface initialization
321 1 // ...see TD_Init( );
322 1 }
323
324 // Set Address GPIFADR[8:0] to PERIPHERAL
325 void Peripheral_SetAddress( WORD gaddr )
326 {
327 1 SYNCDELAY; //
328 1 GPIFADRH = gaddr >> 8;
329 1 SYNCDELAY; //
330 1 GPIFADRL = ( BYTE )gaddr; // setup GPIF address
331 1 }
332
333 // Set EP2GPIF Transaction Count
334 void Peripheral_SetEP2GPIFTC( WORD xfrcnt )
335 {
336 1 SYNCDELAY; //
337 1 EP2GPIFTCH = xfrcnt >> 8; // setup transaction count
338 1 SYNCDELAY; //
339 1 EP2GPIFTCL = ( BYTE )xfrcnt;
340 1 }
341
342 // Set EP4GPIF Transaction Count
343 void Peripheral_SetEP4GPIFTC( WORD xfrcnt )
344 {
345 1 SYNCDELAY; //
346 1 EP4GPIFTCH = xfrcnt >> 8; // setup transaction count
347 1 SYNCDELAY; //
348 1 EP4GPIFTCL = ( BYTE )xfrcnt;
349 1 }
350
351 // Set EP6GPIF Transaction Count
352
353 void Peripheral_SetEP6GPIFTC( WORD xfrcnt )
354 {
355 1 SYNCDELAY; //
356 1 EP6GPIFTCH = xfrcnt >> 8; // setup transaction count
357 1 SYNCDELAY; //
358 1 EP6GPIFTCL = ( BYTE )xfrcnt;
359 1 }
360
361
362 void Peripheral_SetEP6GPIFTCX( WORD xfrcnt )
363 {
364 1 SYNCDELAY; //
C51 COMPILER V7.10 GPIF_MAXSINGLE 09/25/2005 16:17:29 PAGE 7
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -