📄 enchid.lst
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CYASM Version 1.81
(C) 2000 Cypress Semiconductor Corp.
0000 ;******************************************************
0000 ;
0000 ;File: encorhid.asm
0000 ;adapted from Cypress Semiconductor's logo.asm by Jan Axelson
0000 ;Date: 09/25/2000
0000 ;Chip: Cypress Semiconductor CY7C637xx Encore series USB Microcontroller
0000 ;Assembler: cyasm.exe
0000 ;Purpose: demonstrates USB communications with a HID-class device
0000 ;Description:
0000 ;Handles standard USB and HID-class requests.
0000 ;Receives data from the host in Output reports
0000 ;using interrupt transfers on Endpoint 1.
0000 ;Sends data to the host in Input reports
0000 ;using control transfers on Endpoint 0.
0000 ;I used Cypress Semiconductor's logo.asm example code as a base
0000 ;in creating this program.
0000 ;The companion host software is the Visual-Basic project usbhidio.vbp
0000 ;or the Visual C++ project usbhidioc.
0000 ;For more information, visit Lakeview Research at http://www.lvr.com .
0000 ;Send comments, bug reports, etc. to jan@lvr.com .
0000
0000 ; Target: Cypress CY7C63743
0000 ;
0000 ; Overview: There is only one task handled by this
0000 ; firmware, and that is USB.
0000 ;
0000 ; USB
0000 ; At bus reset the USB interface is re-initialized,
0000 ; and the firmware soft reboots. We are then able to
0000 ; handle the standard chapter nine requests on
0000 ; endpoint zero (the control endpoint). After this
0000 ; device enumerates as a HID mouse on the USB, the
0000 ; requests come to endpoint one (the data endpoint).
0000 ; Endpoint one is used to send Input reports.
0000 ; Endpoint zero is used to receive Output reports
0000 ; in Set_Report requests.
0000 ;
0000 ; Pin Connections
0000 ;
0000 ; -------------------
0000 ; | P0[0] P0[4] |
0000 ; | P0[1] P0[5] |
0000 ; | P0[2] P0[6] |
0000 ; | P0[3] P0[7] |
0000 ; | P1[0] P1[1] |
0000 ; | P1[2] P1[3] |
0000 ; | P1[4] P1[5] |
0000 ; | P1[6] P1[7] |
0000 ; GND | VSS D+/SCLK | USB D+ / PS2 SCLK
0000 ; GND | VPP D-/SDATA| USB D- / PS2 SDATA
0000 ; PULLUP | VREG VCC | +5
0000 ; | XTALIN XTALOUT |
0000 ; -------------------
0000 ;
0000 ; Revisions:
0000 ; 9-25-2000 Creation
0000 ;
0000 ;To do (things to be added):
0000 ;Add ability to send and receive Feature reports.
0000 ;Add ability to receive Output reports > 8 bytes.
0000 ;Add ability to receive interrupt Out reports.
0000 ;Move watchdog reset out of 1-ms timer routine.
0000 ;
0000 ;**********************************************************
0000 ;
0000 ; Copyright 2000 Cypress Semiconductor and Lakeview Research
0000 ; Portions of this code are provided by Cypress and by
0000 ; Lakeview Research as a reference. Cypress and Lakeview
0000 ; make no claims or warranties to this firmware's
0000 ; suitability for any application.
0000 ;
0000 ;**********************************************************
0000
0000 ;**************** assembler directives *****************
0000
0000 CPU 63743
0000
0000 XPAGEON
0000
0000
0000 ; processor registers
0000 port0: equ 00h
0000 port1: equ 01h
0000 port2: equ 02h
0000
0000 port0_int: equ 04h
0000 port1_int: equ 05h
0000 port0_int_polarity: equ 06h
0000 port1_int_polarity: equ 07h
0000
0000 port0_mode0: equ 0Ah
0000 port0_mode1: equ 0Bh
0000 port1_mode0: equ 0Ch
0000 port1_mode1: equ 0Dh
0000
0000 usb_address: equ 10h
0000 ep0_count: equ 11h
0000 ep0_mode: equ 12h
0000 ep1_count: equ 13h
0000 ep1_mode: equ 14h
0000 ep2_count: equ 15h
0000 ep2_mode: equ 16h
0000 usb_status: equ 1Fh
0000
0000 global_int: equ 20h
0000 endpoint_int: equ 21h
0000 timer_lsb: equ 24h
0000 timer_msb: equ 25h
0000 watchdog: equ 26h
0000
0000 capturea_rising: equ 40h
0000 capturea_falling: equ 41h
0000 captureb_rising: equ 42h
0000 captureb_falling: equ 43h
0000 capture_config: equ 44h
0000 capture_status: equ 45h
0000
0000 spi_data: equ 60h
0000 spi_control: equ 61h
0000
0000 clock_config: equ F8h
0000 control: equ FFh
0000
0000 ; Port 2 Data Register 0x02 bit assignments
0000 SCLK: equ 20h
0000 DPLUS: equ 20h
0000 SDATA: equ 10h
0000 DMINUS: equ 10h
0000 XTALIN: equ 02h
0000 VREG: equ 01h
0000
0000 ; USB Port status and control register 0x1F bit assignments
0000 PS2_PULLUP: equ 80h
0000 VREG_ENABLE: equ 40h
0000 USB_PS2_MODE: equ 20h
0000 BUS_ACTIVITY: equ 08h
0000 CONTROL2: equ 04h
0000 CONTROL1: equ 02h
0000 CONTROL0: equ 01h
0000
0000 NOT_FORCING: equ 00h
0000 FORCE_K: equ 01h
0000 FORCE_J: equ 02h
0000 FORCE_SE0: equ 03h
0000 FORCEBOTH_LOW: equ 40h
0000 FORCESDATA_LOW: equ 05h
0000 FORCESCLK_LOW: equ 06h
0000 FORCE_HIZ: equ 07h
0000
0000 ; USB Device Address Registers 0x10 bit assignments
0000 ADDRESS_ENABLE: equ 80h
0000 ADDRESS_MASK: equ 7Fh
0000
0000 ; USB Device EP0 Mode Register 0x12
0000 EP0_SETUP: equ 80h
0000 EP0_IN: equ 40h
0000 EP0_OUT: equ 20h
0000 EP0_ACK: equ 10h
0000 MODE_MASK: equ 0Fh
0000
0000 ; USB Device Endpoint Mode Registers 0x14, 0x16
0000 EP_STALL: equ 80h
0000 EP_ACK: equ 10h
0000
0000 ; USB Device Counter Registers 0x11, 0x13, 0x15
0000 DATA_TOGGLE: equ 80h
0000 DATA_VALID: equ 40h
0000 BYTE_COUNT: equ 0Fh
0000
0000 ;Capture Timers Configuration Register 0x44
0000 FIRST_EDGE_HOLD: equ 80h
0000 PRESCALE: equ 70h
0000 PRESCALE2: equ 40h
0000 PRESCALE1: equ 20h
0000 PRESCALE0: equ 10h
0000 CAPTUREB_FALL_INT: equ 08h
0000 CAPTUREB_RISE_INT: equ 04h
0000 CAPTUREA_FALL_INT: equ 02h
0000 CAPTUREA_RISE_INT: equ 01h
0000
0000 ;Capture Timers Status Register 0x45
0000 CAPTUREB_FALL_EVENT: equ 08h
0000 CAPTUREB_RISE_EVENT: equ 04h
0000 CAPTUREA_FALL_EVENT: equ 02h
0000 CAPTUREA_RISE_EVENT: equ 01h
0000
0000 ;Processor Status and Control Register 0xFF
0000 IRQ_PENDING: equ 80h
0000 WDR: equ 40h
0000 USB_RESET: equ 20h
0000 POR_RESET: equ 10h
0000 SUSPEND: equ 08h
0000 INT_ENABLE_SENSE: equ 04h
0000 RUN: equ 01h
0000
0000 ; global interrupt enable register 0x20 bit assignments
0000 WAKEUP_INT: equ 80h
0000 GPIO_INT: equ 40h
0000 CAPTUREB_INT: equ 20h
0000 CAPTUREA_INT: equ 10h
0000 SPI_INT: equ 08h
0000 1MS_INT: equ 04h
0000 128US_INT: equ 02h
0000 USB_RESET_INT: equ 01h
0000
0000 ; USB Endpoint Interrupt Enable Register 0x21 bit assignments
0000 EP2_INT: equ 04h
0000 EP1_INT: equ 02h
0000 EP0_INT: equ 01h
0000
0000 ; SPI Control Register 0x61 bit assignments
0000 TCMP: equ 80h
0000 TBF: equ 40h
0000 MODE1: equ 20h
0000 MODE0: equ 10h
0000 CPOL: equ 08h
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