sh-cache.c

this is ipl loader for hitachi SH4 processor.

/* sh-cache.c: Cache control functions for SH7750
 *
 *  Copyright (C) 2001 KOMORIYA Takeru
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 * See the file "GPL" for more details.
 *
 * Contact to author:
 *   KOMORIYA Takeru, AAF Sendai Lab., Japan
 *   E-mail: [e-mail]
 *      URL: http://chmodx.dyndns.org/aaf/
 */

#include "sh7750.h"
#include "sh-cache.h"
#include "sh-intr.h"

#define CCR_INIT      0x0000898d  /* IIX=1,ICI=1,ICE=1,OIX=1, ORA=0,
				     OCI=1,CB=1, WT=0, OCD=1
				     IC: 8k, OC: 16k
				     P1: Copy-back mode
				     P0,P3: Copy-back mode */
#define CCR_STOP       0x00000808  /* ICI,OCI=1 others=0 */
#define CCR_ENABLE     0x00000101  /* ICE,OCE */
#define OC_ADDRESS_ARRAY 0xf4000000
#define OC_ENTRIES       512
#define CACHE_DIRTY	 2

static void
sh_cache_handle (int c)
{
  unsigned long i, a, data;

  a = CCR;

  if (a & CCR_ENABLE){
    /* Write U=0 to all OC address array to write-back */
    for (i=0; i<OC_ENTRIES; i++)
      {
	data = (*(volatile unsigned int *)(OC_ADDRESS_ARRAY|(i<<5)));
	if (data & CACHE_DIRTY)
	  {
	    data &= ~CACHE_DIRTY;
	    (*(volatile unsigned int *)(OC_ADDRESS_ARRAY|(i<<5))) = data;
	  }
      }
  }
  if (c == CACHE_ENABLE)
    CCR = CCR_INIT;
  else
    CCR = CCR_STOP;
  
  /* 8 instructions for cache wake up */
  __asm__ __volatile__
    ( "nop;nop;nop;nop;nop;nop;nop;nop" );

}

void
sh_cache_control (int c)
{
  void (*entrypoint)(int c);

  intr_disable();

  /* Change Area P1 to P2 */
  entrypoint = (void *)((unsigned long)sh_cache_handle | 0x20000000);
  entrypoint(c); /* call sh_cache_handle() */

  intr_enable();
}