entry.s

this is ipl loader for hitachi SH4 processor.

/* entry.S: Startup program for SH7750
 *          (ROM boot version)
 *
 *  Copyright (C) 2001 KOMORIYA Takeru
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 * See the file "GPL" for more details.
 *
 * Contact to author:
 *   KOMORIYA Takeru, AAF Sendai Lab., Japan
 *   E-mail: [e-mail]
 *      URL: http://chmodx.dyndns.org/aaf/
 */

	.text
	.balign 	4096,0,4096

	.globl start
	.balign 4
start:	
	/* Disable cache */
	mov.l	CCR_A, r1
	mov.l	CCR_DISABLE, r0
	mov.l	r0, @r1
	
	/* Disable SCIF */	
	mov.l	SCSCR_A,r1
	mov	#0,r0
	mov.w	r0,@r1

	mov.l	SCFSR_A,r1
	mov.w	@r1,r0		/* dummy read */
	mov.l	SCFSR_D,r0
	mov.w	r0,@r1

	/* Disable TMU */	
	mov.l	TSTR_A,r1
	mov	#0,r0
	mov.b	r0,@r1

	mov.l	TCOR0_A,r1
	mov.l	TCOR0_D,r0
	mov.l	r0,@r1

	mov.l	TCNT0_A,r1
	mov.l	TCNT0_D,r0
	mov.l	r0,@r1

	mov.l	TCR0_A,r1
	mov	#0,r0
	mov.w	r0,@r1
	
	/* Initialize BSC */		
	mov.l	BCR1_A,r1
	mov.l	BCR1_D,r0
	mov.l	r0,@r1

	mov.l	BCR2_A,r1
	mov.l	BCR2_D,r0
	mov.w	r0,@r1

	mov.l	WCR1_A,r1
	mov.l	WCR1_D,r0
	mov.l	r0,@r1

	mov.l	WCR2_A,r1
	mov.l	WCR2_D,r0
	mov.l	r0,@r1

	mov.l	WCR3_A,r1
	mov.l	WCR3_D,r0
	mov.l	r0,@r1

	mov.l	RTCOR_A,r1
	mov.l	RTCOR_D,r0
	mov.w	r0,@r1

	mov.l	RTCSR_A,r1
	mov.l	RTCSR_D,r0
	mov.w	r0,@r1

	mov.l	MCR_A,r1
	mov.l	MCR_D1,r0
	mov.l	r0,@r1

	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
	mov	#0,r0
	mov.b	r0,@r1

	/* Wait DRAM refresh 30 times */
	mov.l	RFCR_A,r1
	mov.l	RFCR_D,r0
	mov.w	r0,@r1		/* Clear reflesh counter */
	mov	#30,r3
1:
	mov.w	@r1,r0
	extu.w	r0,r2
	cmp/hi	r3,r2
	bf	1b
	nop

	mov.l	MCR_A,r1
	mov.l	MCR_D2,r0	/* MRSET=1*/
	mov.l	r0,@r1

	/* Set SDRAM mode */
	mov.l	SDMR3_A,r1
	mov	#0,r0
	mov.b	r0,@r1

	/* Initialize VBR */
	mov.l	VBR_INIT, r0
	ldc	r0, vbr

	/* SR: MD=1, BL=0, RB=0 */
	mov.l	INITIAL_SR, r0
	ldc	r0, sr

	/* Initialize stack */
	mov.l	INITIAL_STACK, r0
	mov	r0, r15

        /* Copy initial values from ROM to RAM */
	mov.l	ETEXT, r0
	mov.l	INIT_VALUES_START, r1
	mov.l	INIT_VALUES_END, r2
	cmp/eq	r1, r0
	bt	3f
	cmp/eq	r2, r1
	bt	3f
2:	mov.b	@r0+, r4
	mov.b	r4, @r1
	add	#1, r1
	cmp/ge	r1, r2
	bt	2b
	
        /* Initialize BSS */
3:	mov.l	BSS_START, r1
	add	#4, r1
	mov.l	BSS_END, r2
	mov	#0, r0
4:	cmp/hs	r2, r1
	bf/s	4b
	 mov.l	r0, @-r2

	/* Jump to main */
	mov.l	START_MAIN, r0
	jmp	@r0
	 nop

	.align	2
CCR_A:		.long	0xff00001c      /* CCR Address */
CCR_DISABLE:	.long	0x0808
BCR1_A:		.long	0xFF800000	/* BCR1 Address */
BCR1_D:		.long	0x0000000C	/* Area 2,3 SDRAM */
BCR2_A:		.long	0xFF800004	/* BCR2 Address */
BCR2_D:		.long	0xAAF9		/* Area 0,1,4-6:16bit Area 2,3:32bit */
WCR1_A:		.long	0xFF800008	/* WCR1 Address */
WCR1_D:		.long	0x77770711	/* Wait control register */
WCR2_A:		.long	0xFF80000C	/* WCR2 Address */
WCR2_D:		.long	0xFFFE4E48
WCR3_A:		.long	0xFF800010	/* WCR3 Address */
WCR3_D:		.long	0x07777755
RTCOR_A:	.long	0xFF800024	/* RTCOR Address */
RTCOR_D:	.long	0xA540		/* RTCOR Write Code A5h Data 40h */
RTCSR_A:	.long	0xFF80001C	/* RTCSR Address */
RTCSR_D:	.long	0xA510		/* RTCSR Write Code A5h Data 10h*/
SDMR3_A:	.long	0xFF94008c	/* SDMR3 Address */
MCR_A:		.long	0xFF800014	/* MCR Address */
MCR_D1:		.long	0x18094194	/* MRSET:'0' */
MCR_D2:		.long	0x58094194	/* MRSET:'1' */
RFCR_A:		.long	0xFF800028	/* RFCR Address */
RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
SCSCR_A:	.long	0xFFE80008	/* SCSCR Address */
TSTR_A:		.long	0xFFD80004	/* TSTR Address */
TCOR0_A:	.long	0xFFD80008	/* TCOR0 Address */
TCOR0_D:	.long	0xFFFFFFFF	/* TCOR0 Data */
TCNT0_A:	.long	0xFFD8000C	/* TCNT0 Address */
TCNT0_D:	.long	0xFFFFFFFF	/* TCNT0 Data */
TCR0_A:		.long	0xFFD80010	/* TCR0 Address */
SCFSR_A:	.long	0xFFE80010	/* SCFSR Address */
SCFSR_D:	.long	0x0060		/* SCFSR Data */

START_MAIN:	.long	start_main
INITIAL_SR:	.long	0x40000000	/* MD=1, RD=0, BL=0 */
INITIAL_STACK:	.long	__init_stack
VBR_INIT:	.long	start
ETEXT:		.long   __etext
INIT_VALUES_START:
		.long   __init_values_start
INIT_VALUES_END:
		.long   __init_values_end
BSS_START:	.long   __bss_start
BSS_END:	.long   __bss_end

	.balign 	256,0,256
general_exception:
	mov.l	EXPEVT, r2
	bra	exception
	 mov.l	@r2, r2
	.align	2
EXPEVT:	.long	0xff000024

	.balign 	1024,0,1024
tlb_miss:
	mov.l	EXTEVT, r2
	bra	exception
	 mov.l	@r2, r2
	.align	2
EXTEVT:	.long	0xff000024

	.balign 	512,0,512
interrupt:
	mov.l	INTEVT, r2
	bra	exception
	 mov.l	@r2, r2
	.align	2
INTEVT:	.long	0xff000028

exception:
	/* Push registers */
	stc.l	spc,@-r15
	stc.l	ssr,@-r15
	sts.l	pr,@-r15
	sts.l	mach,@-r15
	sts.l	macl,@-r15

	/* Call C function
	   note: assume that registers r8-r14, 
		and fpr* are  preserved in C function
	 */
	shlr2	r2
	shlr2	r2
	shlr	r2
	mov	r2,r1
	shll2	r1
	mov.l	1f, r0
	add	r1, r0
	mov.l	@r0, r0
	jsr	@r0
	 nop

	/* SR.BL = 1 */
	stc	sr, r0
	mov.l	2f, r1
	or	r1, r0
	ldc	r0, sr

	/* Pop registers */
	lds.l	@r15+, macl
	lds.l	@r15+, mach
	lds.l	@r15+, pr
	ldc.l	@r15+, ssr
	ldc.l	@r15+, spc

	/* end of interrupt */
	rte
	 nop
	.align	2
1:	.long	interrupt_table
2:	.long	0xdfffffff