stm32l1xx_rcc.c

VS1003_MP3_SPI_SDHC_FAT32

  tmp = RCC->CFGR & RCC_CFGR_HPRE;
  tmp = tmp >> 4;
  presc = APBAHBPrescTable[tmp]; 
  /* HCLK clock frequency */
  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;

  /* Get PCLK1 prescaler */
  tmp = RCC->CFGR & RCC_CFGR_PPRE1;
  tmp = tmp >> 8;
  presc = APBAHBPrescTable[tmp];
  /* PCLK1 clock frequency */
  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;

  /* Get PCLK2 prescaler */
  tmp = RCC->CFGR & RCC_CFGR_PPRE2;
  tmp = tmp >> 11;
  presc = APBAHBPrescTable[tmp];
  /* PCLK2 clock frequency */
  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
}

/**
  * @}
  */

/** @defgroup RCC_Group3 Peripheral clocks configuration functions
 *  @brief   Peripheral clocks configuration functions 
 *
@verbatim
 ===============================================================================
             ##### Peripheral clocks configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to configure the Peripheral clocks. 
         (#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC 
         (HSE divided by a programmable prescaler).
         (#) After restart from Reset or wakeup from STANDBY, all peripherals are 
             off except internal SRAM, Flash and JTAG. Before to start using a 
             peripheral you have to enable its interface clock. You can do this 
             using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and 
             RCC_APB1PeriphClockCmd() functions.

         (#) To reset the peripherals configuration (to the default state after 
             device reset) you can use RCC_AHBPeriphResetCmd(), 
             RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions.
         (#) To further reduce power consumption in SLEEP mode the peripheral 
             clocks can be disabled prior to executing the WFI or WFE instructions.
             You can do this using RCC_AHBPeriphClockLPModeCmd(), 
             RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() 
             functions.

@endverbatim
  * @{
  */

/**
  * @brief  Configures the RTC and LCD clock (RTCCLK / LCDCLK).
  * @note     As the RTC clock configuration bits are in the RTC domain and write
  *           access is denied to this domain after reset, you have to enable write
  *           access using PWR_RTCAccessCmd(ENABLE) function before to configure
  *           the RTC clock source (to be done once after reset).    
  * @note     Once the RTC clock is configured it can't be changed unless the RTC
  *           is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
  * @note     The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
  *             
  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
  *   This parameter can be one of the following values:
  *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  *     @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
  *     @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
  *     @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
  *     @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
  *       
  * @note     If the LSE or LSI is used as RTC clock source, the RTC continues to
  *           work in STOP and STANDBY modes, and can be used as wakeup source.
  *           However, when the HSE clock is used as RTC clock source, the RTC
  *           cannot be used in STOP and STANDBY modes.
  *             
  * @note     The maximum input clock frequency for RTC is 1MHz (when using HSE as
  *           RTC clock source).
  *                          
  * @retval None
  */
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
{
  uint32_t 	tmpreg = 0;

  /* Check the parameters */
  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
  
  if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)
  { 
    /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
    tmpreg = RCC->CR;

    /* Clear RTCPRE[1:0] bits */
    tmpreg &= ~RCC_CR_RTCPRE;

    /* Configure HSE division factor for RTC clock */
    tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);

    /* Store the new value */
    RCC->CR = tmpreg;
  }
         
  RCC->CSR &= ~RCC_CSR_RTCSEL;
  
  /* Select the RTC clock source */
  RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);
}

/**
  * @brief  Enables or disables the RTC clock.
  * @note   This function must be used only after the RTC clock source was selected
  *         using the RCC_RTCCLKConfig function.
  * @param  NewState: new state of the RTC clock.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_RTCCLKCmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;
}

/**
  * @brief  Forces or releases the RTC peripheral and associated resources reset.
  * @note   This function resets the RTC peripheral, RTC clock source selection
  *         (in RCC_CSR) and the backup registers.
  * @param  NewState: new state of the RTC reset.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_RTCResetCmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;
}

/**
  * @brief  Enables or disables the AHB peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before 
  *         using it.    
  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
  *   This parameter can be any combination of the following values:
  *     @arg RCC_AHBPeriph_GPIOA:         GPIOA clock
  *     @arg RCC_AHBPeriph_GPIOB:         GPIOB clock
  *     @arg RCC_AHBPeriph_GPIOC:         GPIOC clock
  *     @arg RCC_AHBPeriph_GPIOD:         GPIOD clock
  *     @arg RCC_AHBPeriph_GPIOE:         GPIOE clock
  *     @arg RCC_AHBPeriph_GPIOH:         GPIOH clock
  *     @arg RCC_AHBPeriph_GPIOF:         GPIOF clock
  *     @arg RCC_AHBPeriph_GPIOG:         GPIOG clock
  *     @arg RCC_AHBPeriph_CRC:           CRC clock
  *     @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)  
  *     @arg RCC_AHBPeriph_DMA1:          DMA1 clock
  *     @arg RCC_AHBPeriph_DMA2:          DMA2 clock
  *     @arg RCC_AHBPeriph_AES:           AES clock
  *     @arg RCC_AHBPeriph_FSMC:          FSMC clock
  * @param  NewState: new state of the specified peripheral clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
  {
    RCC->AHBENR |= RCC_AHBPeriph;
  }
  else
  {
    RCC->AHBENR &= ~RCC_AHBPeriph;
  }
}

/**
  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before 
  *         using it.
  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
  *   This parameter can be any combination of the following values:
  *     @arg RCC_APB2Periph_SYSCFG: SYSCFG APB2 Clock.
  *     @arg RCC_APB2Periph_TIM9: TIM9 APB2 Clock.
  *     @arg RCC_APB2Periph_TIM10: TIM10 APB2 Clock.
  *     @arg RCC_APB2Periph_TIM11: TIM11 APB2 Clock.
  *     @arg RCC_APB2Periph_ADC1: ADC1 APB2 Clock.
  *     @arg RCC_APB2Periph_SDIO: SDIO APB2 Clock.
  *     @arg RCC_APB2Periph_SPI1: SPI1 APB2 Clock.
  *     @arg RCC_APB2Periph_USART1: USART1 APB2 Clock.
  * @param  NewState: new state of the specified peripheral clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    RCC->APB2ENR |= RCC_APB2Periph;
  }
  else
  {
    RCC->APB2ENR &= ~RCC_APB2Periph;
  }
}

/**
  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before 
  *         using it.
  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
  *   This parameter can be any combination of the following values:
  *     @arg RCC_APB1Periph_TIM2:      TIM2 clock
  *     @arg RCC_APB1Periph_TIM3:      TIM3 clock
  *     @arg RCC_APB1Periph_TIM4:      TIM4 clock
  *     @arg RCC_APB1Periph_TIM5:      TIM5 clock  
  *     @arg RCC_APB1Periph_TIM6:      TIM6 clock
  *     @arg RCC_APB1Periph_TIM7:      TIM7 clock
  *     @arg RCC_APB1Periph_LCD:       LCD clock
  *     @arg RCC_APB1Periph_WWDG:      WWDG clock
  *     @arg RCC_APB1Periph_SPI2:      SPI2 clock
  *     @arg RCC_APB1Periph_SPI3:      SPI3 clock
  *     @arg RCC_APB1Periph_USART2:    USART2 clock
  *     @arg RCC_APB1Periph_USART3:    USART3 clock
  *     @arg RCC_APB1Periph_UART4:     UART4 clock
  *     @arg RCC_APB1Periph_UART5:     UART5 clock  
  *     @arg RCC_APB1Periph_I2C1:      I2C1 clock
  *     @arg RCC_APB1Periph_I2C2:      I2C2 clock
  *     @arg RCC_APB1Periph_USB:       USB clock
  *     @arg RCC_APB1Periph_PWR:       PWR clock
  *     @arg RCC_APB1Periph_DAC:       DAC clock
  *     @arg RCC_APB1Periph_COMP       COMP  clock
  * @param  NewState: new state of the specified peripheral clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    RCC->APB1ENR |= RCC_APB1Periph;
  }
  else
  {
    RCC->APB1ENR &= ~RCC_APB1Periph;
  }
}

/**
  * @brief  Forces or releases AHB peripheral reset.
  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
  *   This parameter can be any combination of the following values:
  *     @arg RCC_AHBPeriph_GPIOA:         GPIOA clock
  *     @arg RCC_AHBPeriph_GPIOB:         GPIOB clock
  *     @arg RCC_AHBPeriph_GPIOC:         GPIOC clock  
  *     @arg RCC_AHBPeriph_GPIOD:         GPIOD clock
  *     @arg RCC_AHBPeriph_GPIOE:         GPIOE clock
  *     @arg RCC_AHBPeriph_GPIOH:         GPIOH clock
  *     @arg RCC_AHBPeriph_GPIOF:         GPIOF clock
  *     @arg RCC_AHBPeriph_GPIOG:         GPIOG clock  
  *     @arg RCC_AHBPeriph_CRC:           CRC clock
  *     @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)  
  *     @arg RCC_AHBPeriph_DMA1:          DMA1 clock
  *     @arg RCC_AHBPeriph_DMA2:          DMA2 clock
  *     @arg RCC_AHBPeriph_AES:           AES clock
  *     @arg RCC_AHBPeriph_FSMC:          FSMC clock  
  * @param  NewState: new state of the specified peripheral reset.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    RCC->AHBRSTR |= RCC_AHBPeriph;
  }
  else
  {
    RCC->AHBRSTR &= ~RCC_AHBPeriph;
  }
}

/**
  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
  *   This parameter can be any combination of the following values:
  *     @arg RCC_APB2Periph_SYSCFG:       SYSCFG clock
  *     @arg RCC_APB2Periph_TIM9:         TIM9 clock      
  *     @arg RCC_APB2Periph_TIM10:        TIM10 clock