stm32l1xx_aes.c

VS1003_MP3_SPI_SDHC_FAT32

/**
  * @brief  Returns the data in DOUTR register processed by AES peripheral.
  * @note   This function must be called four times to get the 128-bit data.
  * @note   When an unexpected read of DINR register is detected, RDERR flag is
  *         set.
  * @retval The processed data.
  */
uint32_t AES_ReadSubData(void)
{
  /* Read Data */
  return AES->DOUTR;
}

/**
  * @brief  Read the Key value.
  * @param  AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which
  *         will contain the key.
  * @note   When the key derivation mode is selected, AES must be disabled
  *         (AES_Cmd(DISABLE)) before reading the decryption key.
  *         Reading the key while the AES is enabled will return unpredictable
  *         value.
  * @retval None
  */
void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)
{
  AES_KeyInitStruct->AES_Key0 = AES->KEYR0;
  AES_KeyInitStruct->AES_Key1 = AES->KEYR1;
  AES_KeyInitStruct->AES_Key2 = AES->KEYR2;
  AES_KeyInitStruct->AES_Key3 = AES->KEYR3;
}

/**
  * @brief  Read the Initialization Vector IV value.
  * @param  AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
  *         will contain the Initialization Vector IV.
  * @note   When the AES is enabled Reading the Initialization Vector IV value
  *         will return 0. The AES must be disabled using AES_Cmd(DISABLE)
  *         to get the right value.
  * @note   When ECB chaining mode is selected, Initialization Vector IV has no
  *         meaning.
  *         When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.
  *         AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
  * @retval None
  */
void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)
{
  AES_IVInitStruct->AES_IV0 = AES->IVR0;
  AES_IVInitStruct->AES_IV1 = AES->IVR1;
  AES_IVInitStruct->AES_IV2 = AES->IVR2;
  AES_IVInitStruct->AES_IV3 = AES->IVR3;
}

/**
  * @}
  */

/** @defgroup AES_Group4 DMA transfers management functions
 *  @brief   DMA transfers management function.
 *
@verbatim
 ===============================================================================
               ##### DMA transfers management functions #####
 ===============================================================================

@endverbatim
  * @{
  */

/**
  * @brief  Configures the AES DMA interface.
  * @param  AES_DMATransfer: Specifies the AES DMA transfer.
  *   This parameter can be one of the following values:
  *     @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.
  *     @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.
  *     @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
  * @param  NewState Indicates the new state of the AES DMA interface.
  *           This parameter can be: ENABLE or DISABLE.
  * @note   The DMA has no action in key derivation mode.
  * @retval None
  */
void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)
{
  /* Check the parameter */
  assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));

  if (NewState != DISABLE)
  {
    /* Enable the DMA transfer */
    AES->CR |= (uint32_t) AES_DMATransfer;
  }
  else
  {
    /* Disable the DMA transfer */
    AES->CR &= (uint32_t)(~AES_DMATransfer);
  }
}

/**
  * @}
  */

/** @defgroup AES_Group5 Interrupts and flags management functions
 *  @brief   Interrupts and flags management functions.
 *
@verbatim

 ===============================================================================
           ##### Interrupts and flags management functions #####
 ===============================================================================
@endverbatim
  * @{
  */

/**
  * @brief  Enables or disables the specified AES interrupt.
  * @param  AES_IT: Specifies the AES interrupt source to enable/disable.
  *     This parameter can be any combinations of the following values:
  *     @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF 
  *                     flag is set an interrupt is generated.
  *     @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error
  *                      flags (RDERR) or write error flag (WRERR) is set,
  *                      an interrupt is generated.
  * @param  NewState: The new state of the AES interrupt source.
  *                   This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  assert_param(IS_AES_IT(AES_IT));

  if (NewState != DISABLE)
  {
    AES->CR |= (uint32_t) AES_IT;    /**< AES_IT Enable */
  }
  else
  {
    AES->CR &= (uint32_t)(~AES_IT);  /**< AES_IT Disable */
  }
}

/**
  * @brief  Checks whether the specified AES flag is set or not.
  * @param  AES_FLAG specifies the flag to check.
  *   This parameter can be one of the following values:
  *     @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when
  *                        he computation phase is completed.
  *     @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read
  *                          operation of DOUTR register is detected.
  *     @arg AES_FLAG_WRERR: Write Error Flag  is set when an unexpected write
  *                          operation in DINR is detected.
  * @retval FlagStatus (SET or RESET)
  */
FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)
{
  FlagStatus bitstatus = RESET;

  /* Check parameters */
  assert_param(IS_AES_FLAG(AES_FLAG));

  if ((AES->SR & AES_FLAG) != (uint32_t)RESET)
  {
    bitstatus = SET;
  }
  else
  {
    bitstatus = RESET;
  }
    
  /* Return the AES_FLAG status */
  return  bitstatus;
}

/**
  * @brief  Clears the AES flags.
  * @param  AES_FLAG: specifies the flag to clear.
  *         This parameter can be:
  *     @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC
  *                        bit in CR register.
  *     @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in 
  *                          CR register.
  *     @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in
  *                          CR register.
  * @retval None
  */
void AES_ClearFlag(uint32_t AES_FLAG)
{
  /* Check the parameters */
  assert_param(IS_AES_FLAG(AES_FLAG));

  /* Check if AES_FLAG is AES_FLAG_CCF */
  if (AES_FLAG == AES_FLAG_CCF)
  {
    /* Clear CCF flag by setting CCFC bit */
    AES->CR |= (uint32_t) AES_CR_CCFC;
  }
  else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
  {
    /* Clear RDERR and WRERR flags by setting ERRC bit */
    AES->CR |= (uint32_t) AES_CR_ERRC;
  }
}

/**
  * @brief  Checks whether the specified AES interrupt has occurred or not.
  * @param  AES_IT: Specifies the AES interrupt pending bit to check.
  *         This parameter can be:
  *     @arg AES_IT_CC: Computation Complete Interrupt.
  *     @arg AES_IT_ERR: Error Interrupt.
  * @retval ITStatus The new state of AES_IT (SET or RESET).
  */
ITStatus AES_GetITStatus(uint32_t AES_IT)
{
  ITStatus itstatus = RESET;
  uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;

  /* Check parameters */
  assert_param(IS_AES_GET_IT(AES_IT));

  cciebitstatus = AES->CR & AES_CR_CCIE;
  ccfbitstatus =  AES->SR & AES_SR_CCF;

  /* Check if AES_IT is AES_IT_CC */
  if (AES_IT == AES_IT_CC)
  {
    /* Check the status of the specified AES interrupt */
    if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))
    {
      /* Interrupt occurred */
      itstatus = SET;
    }
    else
    {
      /* Interrupt didn't occur */
      itstatus = RESET;
    }
  }
  else /* AES_IT is AES_IT_ERR */
  {
    /* Check the status of the specified AES interrupt */
    if ((AES->CR & AES_CR_ERRIE) != RESET)
    {
      /* Check if WRERR or RDERR flags are set */
      if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)
      {
        /* Interrupt occurred */
        itstatus = SET;
      }
      else
      {
        /* Interrupt didn't occur */
        itstatus = RESET;
      }
    }
    else
    {
      /* Interrupt didn't occur */
      itstatus = (ITStatus) RESET;
    }
  }

  /* Return the AES_IT status */
  return itstatus;
}

/**
  * @brief  Clears the AES's interrupt pending bits.
  * @param  AES_IT: specifies the interrupt pending bit to clear.
  *   This parameter can be any combinations of the following values:
  *     @arg AES_IT_CC: Computation Complete Interrupt.
  *     @arg AES_IT_ERR: Error Interrupt.
  * @retval None
  */
void AES_ClearITPendingBit(uint32_t AES_IT)
{
  /* Check the parameters */
  assert_param(IS_AES_IT(AES_IT));

  /* Clear the interrupt pending bit */
  AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);
}

/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/