stm32l1xx_aes.c

VS1003_MP3_SPI_SDHC_FAT32

/**
  ******************************************************************************
  * @file    stm32l1xx_aes.c
  * @author  MCD Application Team
  * @version V1.1.0
  * @date    24-January-2012
  * @brief   This file provides firmware functions to manage the following 
  *          functionalities of the AES peripheral:           
  *           + Configuration
  *           + Read/Write operations
  *           + DMA transfers management  
  *           + Interrupts and flags management
  * 
  *  @verbatim
 ===============================================================================
                        ##### AES Peripheral features #####
 ===============================================================================
....[..]
   (#) The Advanced Encryption Standard hardware accelerator (AES) can be used
       to both encipher and decipher data using AES algorithm.
   (#) The AES supports 4 operation modes:
       (++) Encryption: It consumes 214 clock cycle when processing one 128-bit block
       (++) Decryption: It consumes 214 clock cycle when processing one 128-bit block
       (++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block
       (++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk
   (#) Moreover 3 chaining modes are supported:
       (++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately
       (++) Cipher block chaining (CBC): Each block is XORed with the previous block
       (++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the
          plain text to give the cipher text
  (#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.
  (#) The AES peripheral supports write/read error handling with interrupt capability.
  (#) Automatic data flow control with support of direct memory access (DMA) using
      2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data
      (DMA2 Channel3).

                      ##### How to use this driver #####
 ===============================================================================
    [..]
        (#) AES AHB clock must be enabled to get write access to AES registers 
            using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).
        (#) Initialize the key using AES_KeyInit().
        (#) Configure the AES operation mode using AES_Init().
        (#) If required, enable interrupt source using AES_ITConfig() and
            enable the AES interrupt vector using NVIC_Init().
        (#) If required, when using the DMA mode.
            (##) Configure the DMA using DMA_Init().
            (##) Enable DMA requests using AES_DMAConfig().
        (#) Enable the AES peripheral using AES_Cmd().
    @endverbatim
  
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
  * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
  *
  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_aes.h"
#include "stm32l1xx_rcc.h"

/** @addtogroup STM32L1xx_StdPeriph_Driver
  * @{
  */

/** @defgroup AES 
  * @brief AES driver modules
  * @{
  */ 

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define CR_CLEAR_MASK  ((uint32_t)0xFFFFFF81)

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup AES_Private_Functions
  * @{
  */

/** @defgroup AES_Group1 Initialization and configuration
 *  @brief   Initialization and configuration.
 *
@verbatim
 ===============================================================================
                ##### Initialization and configuration #####
 ===============================================================================

@endverbatim
  * @{
  */  

  /**
  * @brief  Deinitializes AES peripheral registers to their default reset values.
  * @param  None
  * @retval None
  */
void AES_DeInit(void)
{
  /* Enable AES reset state */
  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);
  /* Release AES from reset state */
  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);
}

/**
  * @brief  Initializes the AES peripheral according to the specified parameters
  *         in the AES_InitStruct:
  *           - AES_Operation: specifies the operation mode (encryption, decryption...).
  *           - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
  *           - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
  * @note   If AES is already enabled, use AES_Cmd(DISABLE) before setting the new 
  *         configuration (When AES is enabled, setting configuration is forbidden).
  * @param  AES_InitStruct: pointer to an AES_InitTypeDef structure that contains 
  *         the configuration information for AES peripheral.
  * @retval None
  */
void AES_Init(AES_InitTypeDef* AES_InitStruct)
{
  uint32_t tmpreg = 0;
  
  /* Check the parameters */
  assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));
  assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));
  assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));

  /* Get AES CR register value */
  tmpreg = AES->CR;
  
  /* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */
  tmpreg &= (uint32_t)CR_CLEAR_MASK;
  
  tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);

  AES->CR = (uint32_t) tmpreg;
}

/**
  * @brief  Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
  * @param  AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that
  *         contains the configuration information for the specified AES Keys.
  * @note   This function must be called while the AES is disabled.
  * @note   In encryption, key derivation and key derivation + decryption modes,
  *         AES_KeyInitStruct must contain the encryption key.
  *         In decryption mode, AES_KeyInitStruct must contain the decryption key.
  * @retval None
  */
void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
{
  AES->KEYR0 = AES_KeyInitStruct->AES_Key0;
  AES->KEYR1 = AES_KeyInitStruct->AES_Key1;
  AES->KEYR2 = AES_KeyInitStruct->AES_Key2;
  AES->KEYR3 = AES_KeyInitStruct->AES_Key3;
}

/**
  * @brief  Initializes the AES Initialization Vector IV according to 
  *         the specified parameters in the AES_IVInitStruct.
  * @param  AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that
  *         contains the configuration information for the specified AES IV.
  * @note   When ECB chaining mode is selected, Initialization Vector IV has no
  *         meaning.
  *         When CTR chaining mode is selected, AES_IV0 contains the CTR value.
  *         AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
  * @retval None
  */
void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)
{
  AES->IVR0 = AES_IVInitStruct->AES_IV0;
  AES->IVR1 = AES_IVInitStruct->AES_IV1;
  AES->IVR2 = AES_IVInitStruct->AES_IV2;
  AES->IVR3 = AES_IVInitStruct->AES_IV3;
}

/**
  * @brief  Enable or disable the AES peripheral.
  * @param  NewState: new state of the AES peripheral.
  *         This parameter can be: ENABLE or DISABLE.
  * @note   The key must be written while AES is disabled.
  * @retval None
  */
void AES_Cmd(FunctionalState NewState)
{
  /* Check the parameter */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    /* Enable the AES peripheral */
    AES->CR |= (uint32_t) AES_CR_EN;   /**< AES Enable */
  }
  else
  {
    /* Disable the AES peripheral */
    AES->CR &= (uint32_t)(~AES_CR_EN);  /**< AES Disable */
  }
}

/**
  * @}
  */

/** @defgroup AES_Group2 Structures initialization functions
 *  @brief   Structures initialization.
 *
@verbatim
 ===============================================================================
              ##### Structures initialization functions #####
 ===============================================================================

@endverbatim
  * @{
  */

/**
  * @brief  Fills each AES_InitStruct member with its default value.
  * @param  AES_InitStruct: pointer to an AES_InitTypeDef structure which will 
  *         be initialized.
  * @retval None
  */
void AES_StructInit(AES_InitTypeDef* AES_InitStruct)
{
  AES_InitStruct->AES_Operation = AES_Operation_Encryp;
  AES_InitStruct->AES_Chaining = AES_Chaining_ECB;
  AES_InitStruct->AES_DataType = AES_DataType_32b;
}

/**
  * @brief  Fills each AES_KeyInitStruct member with its default value.
  * @param  AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which 
  *         will be initialized.
  * @retval None
  */
void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
{
  AES_KeyInitStruct->AES_Key0 = 0x00000000;
  AES_KeyInitStruct->AES_Key1 = 0x00000000;
  AES_KeyInitStruct->AES_Key2 = 0x00000000;
  AES_KeyInitStruct->AES_Key3 = 0x00000000;
}

/**
  * @brief  Fills each AES_IVInitStruct member with its default value.
  * @param  AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
  *         will be initialized.
  * @retval None
  */
void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)
{
  AES_IVInitStruct->AES_IV0 = 0x00000000;
  AES_IVInitStruct->AES_IV1 = 0x00000000;
  AES_IVInitStruct->AES_IV2 = 0x00000000;
  AES_IVInitStruct->AES_IV3 = 0x00000000;
}

/**
  * @}
  */

/** @defgroup AES_Group3 AES Read and Write
 *  @brief   AES Read and Write.
 *
@verbatim
 ===============================================================================
                  ##### AES Read and Write functions #####
 ===============================================================================

@endverbatim
  * @{
  */

/**
  * @brief  Write data in DINR register to be processed by AES peripheral.
  * @note   To process 128-bit data (4 * 32-bit), this function must be called
  *         four times to write the 128-bit data in the 32-bit register DINR.
  * @note   When an unexpected write to DOUTR register is detected, WRERR flag is
  *         set.
  * @param  Data: The data to be processed.
  * @retval None
  */
void AES_WriteSubData(uint32_t Data)
{
  /* Write Data */
  AES->DINR = Data;
}