stm32l1xx_adc.c

VS1003_MP3_SPI_SDHC_FAT32

  /* Set the Analog watchdog channel */
  tmpreg |= ADC_Channel;
  /* Store the new register value */
  ADCx->CR1 = tmpreg;
}

/**
  * @}
  */

/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function
 *  @brief   Temperature Sensor & Vrefint (Voltage Reference internal) management function.
 *
@verbatim   
 =========================================================================================
 ##### Temperature Sensor and Vrefint (Voltage Reference internal) management function #####
 =========================================================================================
    [..] This section provides a function allowing to enable/ disable the internal 
         connections between the ADC and the Temperature Sensor and the Vrefint 
         source.
    [..] A typical configuration to get the Temperature sensor and Vrefint channels 
         voltages is done following these steps :
         (#) Enable the internal connection of Temperature sensor and Vrefint sources 
             with the ADC channels using ADC_TempSensorVrefintCmd() function.
         (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using 
             ADC_RegularChannelConfig() or  ADC_InjectedChannelConfig() functions.
         (#) Get the voltage values, using ADC_GetConversionValue() or 
             ADC_GetInjectedConversionValue().
@endverbatim
  * @{
  */
  
/**
  * @brief  Enables or disables the temperature sensor and Vrefint channel.
  * @param  NewState: new state of the temperature sensor and Vref int channels.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_TempSensorVrefintCmd(FunctionalState NewState)                
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    /* Enable the temperature sensor and Vrefint channel*/
    ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
  }
  else
  {
    /* Disable the temperature sensor and Vrefint channel*/
    ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
  }
}

/**
  * @}
  */

/** @defgroup ADC_Group5 Regular Channels Configuration functions
 *  @brief   Regular Channels Configuration functions.
 *
@verbatim   
 ===============================================================================
            ##### Regular Channels Configuration functions #####
 ===============================================================================
    [..] This section provides functions allowing to manage the ADC regular channels,
         it is composed of 2 sub sections :
         (#) Configuration and management functions for regular channels: This 
             subsection provides functions allowing to configure the ADC regular 
             channels :
             (++) Configure the rank in the regular group sequencer for each channel.
             (++) Configure the sampling time for each channel.
             (++) select the conversion Trigger for regular channels.
             (++) select the desired EOC event behavior configuration.
             (++) Activate the continuous Mode  (*).
             (++) Activate the Discontinuous Mode.
             -@@- Please Note that the following features for regular channels are 
                  configurated using the ADC_Init() function : 
                  (+@@) scan mode activation.
                  (+@@) continuous mode activation (**).
                  (+@@) External trigger source.
                  (+@@) External trigger edge.
                  (+@@) number of conversion in the regular channels group sequencer.
             -@@- (*) and (**) are performing the same configuration.
         (#) Get the conversion data: This subsection provides an important function 
             in the ADC peripheral since it returns the converted data of the current 
             regular channel. When the Conversion value is read, the EOC Flag is 
             automatically cleared.
@endverbatim
  * @{
  */

/**
  * @brief  Configures for the selected ADC regular channel its corresponding
  *         rank in the sequencer and its sampling time.
  * @param  ADCx: where x can be 1 to select the ADC peripheral.
  * @param  ADC_Channel: the ADC channel to configure.
  *   This parameter can be one of the following values:
  *     @arg ADC_Channel_0: ADC Channel0 selected
  *     @arg ADC_Channel_1: ADC Channel1 selected
  *     @arg ADC_Channel_2: ADC Channel2 selected
  *     @arg ADC_Channel_3: ADC Channel3 selected
  *     @arg ADC_Channel_4: ADC Channel4 selected
  *     @arg ADC_Channel_5: ADC Channel5 selected
  *     @arg ADC_Channel_6: ADC Channel6 selected
  *     @arg ADC_Channel_7: ADC Channel7 selected
  *     @arg ADC_Channel_8: ADC Channel8 selected
  *     @arg ADC_Channel_9: ADC Channel9 selected
  *     @arg ADC_Channel_10: ADC Channel10 selected
  *     @arg ADC_Channel_11: ADC Channel11 selected
  *     @arg ADC_Channel_12: ADC Channel12 selected
  *     @arg ADC_Channel_13: ADC Channel13 selected
  *     @arg ADC_Channel_14: ADC Channel14 selected
  *     @arg ADC_Channel_15: ADC Channel15 selected
  *     @arg ADC_Channel_16: ADC Channel16 selected
  *     @arg ADC_Channel_17: ADC Channel17 selected
  *     @arg ADC_Channel_18: ADC Channel18 selected 
  *     @arg ADC_Channel_19: ADC Channel19 selected
  *     @arg ADC_Channel_20: ADC Channel20 selected
  *     @arg ADC_Channel_21: ADC Channel21 selected
  *     @arg ADC_Channel_22: ADC Channel22 selected
  *     @arg ADC_Channel_23: ADC Channel23 selected
  *     @arg ADC_Channel_24: ADC Channel24 selected
  *     @arg ADC_Channel_25: ADC Channel25 selected
  *     @arg ADC_Channel_27: ADC Channel27 selected
  *     @arg ADC_Channel_28: ADC Channel28 selected
  *     @arg ADC_Channel_29: ADC Channel29 selected
  *     @arg ADC_Channel_30: ADC Channel30 selected
  *     @arg ADC_Channel_31: ADC Channel31 selected 
  *     @arg ADC_Channel_0b: ADC Channel0b selected
  *     @arg ADC_Channel_1b: ADC Channel1b selected
  *     @arg ADC_Channel_2b: ADC Channel2b selected
  *     @arg ADC_Channel_3b: ADC Channel3b selected
  *     @arg ADC_Channel_6b: ADC Channel6b selected
  *     @arg ADC_Channel_7b: ADC Channel7b selected
  *     @arg ADC_Channel_8b: ADC Channel8b selected
  *     @arg ADC_Channel_9b: ADC Channel9b selected
  *     @arg ADC_Channel_10b: ADC Channel10b selected
  *     @arg ADC_Channel_11b: ADC Channel11b selected
  *     @arg ADC_Channel_12b: ADC Channel12b selected   
  * @param  Rank: The rank in the regular group sequencer. This parameter
  *               must be between 1 to 28.
  * @param  ADC_SampleTime: The sample time value to be set for the selected 
  *         channel.
  *   This parameter can be one of the following values:
  *     @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
  *     @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
  *     @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
  *     @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles	
  *     @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles	
  *     @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles	
  *     @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles	
  *     @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles	
  * @retval None
  */
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
{
  uint32_t tmpreg1 = 0, tmpreg2 = 0;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_CHANNEL(ADC_Channel));
  assert_param(IS_ADC_REGULAR_RANK(Rank));
  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));

  /* If ADC_Channel_30 or ADC_Channel_31 is selected */
  if (ADC_Channel > ADC_Channel_29)
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SMPR0;
    /* Calculate the mask to clear */
    tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));
    /* Clear the old sample time */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));
    /* Set the new sample time */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SMPR0 = tmpreg1;
  }
  /* If ADC_Channel_20 ... ADC_Channel_29 is selected */
  else if (ADC_Channel > ADC_Channel_19)
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SMPR1;
    /* Calculate the mask to clear */
    tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));
    /* Clear the old sample time */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));
    /* Set the new sample time */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SMPR1 = tmpreg1;
  }
  /* If ADC_Channel_10 ... ADC_Channel_19 is selected */
  else if (ADC_Channel > ADC_Channel_9)
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SMPR2;
    /* Calculate the mask to clear */
    tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));
    /* Clear the old sample time */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
    /* Set the new sample time */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SMPR2 = tmpreg1;
  }
  else /* ADC_Channel include in ADC_Channel_[0..9] */
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SMPR3;
    /* Calculate the mask to clear */
    tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);
    /* Clear the old sample time */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
    /* Set the new sample time */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SMPR3 = tmpreg1;
  }
  /* For Rank 1 to 6 */
  if (Rank < 7)
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SQR5;
    /* Calculate the mask to clear */
    tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));
    /* Clear the old SQx bits for the selected rank */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
    /* Set the SQx bits for the selected rank */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SQR5 = tmpreg1;
  }
  /* For Rank 7 to 12 */
  else if (Rank < 13)
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SQR4;
    /* Calculate the mask to clear */
    tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));
    /* Clear the old SQx bits for the selected rank */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
    /* Set the SQx bits for the selected rank */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SQR4 = tmpreg1;
  }  
  /* For Rank 13 to 18 */
  else if (Rank < 19)
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SQR3;
    /* Calculate the mask to clear */
    tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));
    /* Clear the old SQx bits for the selected rank */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
    /* Set the SQx bits for the selected rank */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SQR3 = tmpreg1;
  }
    
  /* For Rank 19 to 24 */
  else if (Rank < 25)
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SQR2;
    /* Calculate the mask to clear */
    tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));
    /* Clear the old SQx bits for the selected rank */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));
    /* Set the SQx bits for the selected rank */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SQR2 = tmpreg1;
  }   
  
  /* For Rank 25 to 28 */
  else
  {
    /* Get the old register value */
    tmpreg1 = ADCx->SQR1;
    /* Calculate the mask to clear */
    tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));
    /* Clear the old SQx bits for the selected rank */
    tmpreg1 &= ~tmpreg2;
    /* Calculate the mask to set */
    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));
    /* Set the SQx bits for the selected rank */
    tmpreg1 |= tmpreg2;
    /* Store the new register value */
    ADCx->SQR1 = tmpreg1;
  }
}

/**
  * @brief  Enables the selected ADC software start conversion of the regular channels.
  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
  * @retval None
  */
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
{
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));

  /* Enable the selected ADC conversion for regular group */
  ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}

/**
  * @brief  Gets the selected ADC Software start regular conversion Status.
  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
  * @retval The new state of ADC software start conversion (SET or RESET).