stm32l1xx_sdio.c

VS1003_MP3_SPI_SDHC_FAT32

/**
  ******************************************************************************
  * @file    stm32l1xx_sdio.c
  * @author  MCD Application Team
  * @version V1.1.0
  * @date    24-January-2012
  * @brief   This file provides firmware functions to manage the following 
  *          functionalities of the SDIO peripheral:
  *           + Initialization 
  *           + Interrupts and flags management
  *
  *  @verbatim
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
    (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
       (PLLVCO) througth a fixed divider by 2.
       Before to start working with SDIO peripheral make sure that the PLLVCO is 
       well configured to 96MHz. 
       The SDIO peripheral uses two clock signals: 
       (++) SDIO adapter clock (SDIOCLK = 48 MHz).
       (++) APB2 bus clock (PCLK2).
            PCLK2 and SDIO_CK clock frequencies must respect the following 
            condition: Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)).
    (#) Enable peripheral clock using 
        RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). 
    (#) According to the SDIO mode, enable the GPIO clocks using
        RCC_AHBPeriphClockCmd() function.
        The I/O can be one of the following configurations: 
        (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. 
        (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. 
        (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].

    (#) Peripheral's alternate function:  
        (++) Connect the pin to the desired peripherals' Alternate  
             Function (AF) using GPIO_PinAFConfig() function.
        (++) Configure the desired pin in alternate function by: 
             GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
        (++) Select the type, pull-up/pull-down and output speed via  
             GPIO_PuPd, GPIO_OType and GPIO_Speed members.
        (++) Call GPIO_Init() function.

    (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,  
        hardware, flow control and the Clock Divider using the SDIO_Init() 
        function. 
    (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)  
        function.           
    (#) Enable the clock using the SDIO_ClockCmd() function. 
    (#) Enable the NVIC and the corresponding interrupt using the function  
        SDIO_ITConfig() if you need to use interrupt mode.  
    (#) When using the DMA mode
        (++) Configure the DMA using DMA_Init() function.
        (++) Active the needed channel Request using SDIO_DMACmd() function.
    (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
    (#) To control the CPSM (Command Path State Machine) and send commands to the
        card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and 
        SDIO_GetResponse() functions. First, user has to fill the command 
        structure (pointer to SDIO_CmdInitTypeDef) according to the selected 
        command to be sent. The parameters that should be filled are: 
        (++) Command Argument.
        (++) Command Index.
        (++) Command Response type.
        (++) Command Wait.
        (++) CPSM Status (Enable or Disable).
        To check if the command is well received, read the SDIO_CMDRESP register 
        using the SDIO_GetCommandResponse(). The SDIO responses registers 
        (SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function. 
    (#) To control the DPSM (Data Path State Machine) and send/receive  
        data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
        SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.

    *** Read Operations *** 
    ----------------------- 
      [..]
      (#) First, user has to fill the data structure (pointer to 
          SDIO_DataInitTypeDef) according to the selected data type to be received. 
          The parameters that should be filled are:
          (++) Data TimeOut.
          (++) Data Length.
          (++) Data Block size.
          (++) Data Transfer direction: should be from card (To SDIO).
          (++) Data Transfer mode.
          (++) DPSM Status (Enable or Disable).
      (#) Configure the SDIO resources to receive the data from the card 
          according to selected transfer mode (Refer to Step 8, 9 and 10).
      (#) Send the selected Read command (refer to step 11).
      (#) Use the SDIO flags/interrupts to check the transfer status.
 
  *** Write Operations *** 
  ------------------------ 
    [..]
    (#) First, user has to fill the data structure (pointer to
        SDIO_DataInitTypeDef) according to the selected data type to be received. 
        The parameters that should be filled are: 
        (++) Data TimeOut.
        (++) Data Length.
        (++) Data Block size.
        (++) Data Transfer direction:  should be to card (To CARD).
        (++) Data Transfer mode.
        (++) DPSM Status (Enable or Disable).
    (#) Configure the SDIO resources to send the data to the card 
        according to selected transfer mode (Refer to Step 8, 9 and 10).
    (#) Send the selected Write command (refer to step 11).
    (#) Use the SDIO flags/interrupts to check the transfer status.

  @endverbatim
  *
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
  * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
  *
  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  ******************************************************************************
  */ 

/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_sdio.h"
#include "stm32l1xx_rcc.h"

/** @addtogroup STM32L1xx_StdPeriph_Driver
  * @{
  */

/** @defgroup SDIO 
  * @brief SDIO driver modules
  * @{
  */ 

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/ 

/* ------------ SDIO registers bit address in the alias region ----------- */
#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)

/* --- CLKCR Register ---*/

/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
#define CLKEN_BitNumber           0x08
#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))

/* --- CMD Register ---*/

/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
#define SDIOSUSPEND_BitNumber     0x0B
#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))

/* Alias word address of ENCMDCOMPL bit */
#define ENCMDCOMPL_BitNumber      0x0C
#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))

/* Alias word address of NIEN bit */
#define NIEN_BitNumber            0x0D
#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))

/* Alias word address of ATACMD bit */
#define ATACMD_BitNumber          0x0E
#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))

/* --- DCTRL Register ---*/

/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
#define DMAEN_BitNumber           0x03
#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))

/* Alias word address of RWSTART bit */
#define RWSTART_BitNumber         0x08
#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))

/* Alias word address of RWSTOP bit */
#define RWSTOP_BitNumber          0x09
#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))

/* Alias word address of RWMOD bit */
#define RWMOD_BitNumber           0x0A
#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))

/* Alias word address of SDIOEN bit */
#define SDIOEN_BitNumber          0x0B
#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))

/* ---------------------- SDIO registers bit mask ------------------------ */

/* --- CLKCR Register ---*/

/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 

/* --- PWRCTRL Register ---*/

/* SDIO PWRCTRL Mask */
#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)

/* --- DCTRL Register ---*/

/* SDIO DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)

/* --- CMD Register ---*/

/* CMD Register clear mask */
#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)

/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup SDIO_Private_Functions
  * @{
  */

/** @defgroup SDIO_Group1 Initialization and Configuration functions
 *  @brief   Initialization and Configuration functions 
 *
 @verbatim
  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================

@endverbatim
  * @{
  */

/**
  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
  * @param  None
  * @retval None
  */
void SDIO_DeInit(void)
{
  RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
  RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);  
}

/**
  * @brief  Initializes the SDIO peripheral according to the specified 
  *   parameters in the SDIO_InitStruct.
  * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
  *   that contains the configuration information for the SDIO peripheral.
  * @retval None
  */
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
{
  uint32_t tmpreg = 0;
    
  /* Check the parameters */
  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
   
/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
  /* Get the SDIO CLKCR value */
  tmpreg = SDIO->CLKCR;
  
  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
  tmpreg &= CLKCR_CLEAR_MASK;
  
  /* Set CLKDIV bits according to SDIO_ClockDiv value */
  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
  /* Set BYPASS bit according to SDIO_ClockBypass value */
  /* Set WIDBUS bits according to SDIO_BusWide value */
  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
  
  /* Write to SDIO CLKCR */
  SDIO->CLKCR = tmpreg;
}

/**
  * @brief  Fills each SDIO_InitStruct member with its default value.
  * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
  *   will be initialized.
  * @retval None
  */
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
{
  /* SDIO_InitStruct members default value */
  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
}

/**
  * @brief  Enables or disables the SDIO Clock.
  * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SDIO_ClockCmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
}

/**
  * @brief  Sets the power status of the controller.
  * @param  SDIO_PowerState: new state of the Power state. 
  *   This parameter can be one of the following values:
  *     @arg SDIO_PowerState_OFF: SDIO Power OFF.
  *     @arg SDIO_PowerState_ON: SDIO Power ON.
  * @retval None
  */
void SDIO_SetPowerState(uint32_t SDIO_PowerState)