cs8900a.h

Freescale IMX31 ADS CS8900a Head file, it is very important

//-----------------------------------------------------------------------------
//
//  Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
//  Use of this source code is subject to the terms of the Microsoft end-user
//  license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
//  If you did not accept the terms of the EULA, you are not authorized to use
//  this source code. For a copy of the EULA, please see the LICENSE.RTF on
//  your install media.
//
//-----------------------------------------------------------------------------
//
//	Copyright (C) 2004,	Motorola Inc. All Rights Reserved
//
//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
//  THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//  BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//  FREESCALE SEMICONDUCTOR, INC.
//
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//
//  File:  cs8900a.h
//
//  Implementation of CS8900 Driver
//
//  This file implements header file for CS8900.
//
//------------------------------------------------------------------------------

#ifndef _SRC_DRIVERS_CS8900_CS8900A_H

#define _SRC_DRIVERS_CS8900_CS8900A_H

#include <ndis.h>
#include <ntddndis.h>  // defines OID's
#include <Linklist.h>
#include <windows.h>
#include <nkintr.h>
#include <Winbase.h>

#include "bsp.h"

//------------------------------------------------------------------------------
// Defines
//------------------------------------------------------------------------------

// The Version of NDIS that the driver is compatible with
#define CS8900A_NDIS_MAJOR_VERSION 4
#define CS8900A_NDIS_MINOR_VERSION 0

#define UNSPECIFIED (-1)

#define TRUE        1
#define FALSE       0
#define SUCCESS     0
#define FAILURE     1

// 8 16bits register mapped in CS8900 I/O operation, therefore 16 bytes
#define  CS8900_IOSPACE_OPERATION_SIZE     16

#define MAXIMUM_TRANSMIT_PACKET     3


// Hash creation constants.
//
#define CRC_PRIME           0xFFFFFFFF;
#define CRC_POLYNOMIAL      0x04C11DB6;


// Receive buffer status
#define RXBUF_FREE          0x0000
#define RXBUF_ALLOCATED     0x0001
#define RXBUF_LOANED        0x0002


// Config Flags in cs_softc
#define CFGFLG_MEM_MODE     0x0001
#define CFGFLG_USE_SA       0x0002
#define CFGFLG_IOCHRDY      0x0004
#define CFGFLG_DCDC_POL     0x0008
#define CFGFLG_FDX          0x0010
#define CFGFLG_NOT_EEPROM   0x8000


// Media Type in cs_softc
#define MEDIA_AUI           0x0001           // AUI
#define MEDIA_10BASE2       0x0002           // BNC
#define MEDIA_10BASET       0x0003           // RJ45


// IO Port Offsets
#define PORT_RXTX_DATA     0x0000
#define PORT_RXTX_DATA_1   0x0002
#define PORT_TX_CMD        0x0004
#define PORT_TX_LENGTH     0x0006
#define PORT_ISQ           0x0008
#define PORT_PKTPG_PTR     0x000A
#define PORT_PKTPG_DATA    0x000C
#define PORT_PKTPG_DATA_1  0x000E


// PacketPage Offsets
#define PKTPG_EISA_NUM     0x0000
#define PKTPG_PRODUCT_ID   0x0002
#define PKTPG_IO_BASE      0x0020
#define PKTPG_INT_NUM      0x0022
#define PKTPG_MEM_BASE     0x002C
#define PKTPG_BOOTPROM_BASE     0x0030
#define PKTPG_BOOTPROM_MASK     0x0034
#define PKTPG_EEPROM_CMD   0x0040
#define PKTPG_EEPROM_DATA  0x0042
#define PKTPG_RX_CFG       0x0102
#define PKTPG_RX_CTL       0x0104
#define PKTPG_TX_CFG       0x0106
#define PKTPG_BUF_CFG      0x010A
#define PKTPG_LINE_CTL     0x0112
#define PKTPG_SELF_CTL     0x0114
#define PKTPG_BUS_CTL      0x0116
#define PKTPG_TEST_CTL     0x0118
#define PKTPG_ISQ          0x0120
#define PKTPG_RX_EVENT     0x0124
#define PKTPG_TX_EVENT     0x0128
#define PKTPG_BUF_EVENT    0x012C
#define PKTPG_RX_MISS      0x0130
#define PKTPG_TX_COL       0x0132
#define PKTPG_LINE_ST      0x0134
#define PKTPG_SELF_ST      0x0136
#define PKTPG_BUS_ST       0x0138
#define PKTPG_TX_CMD       0x0144
#define PKTPG_TX_LENGTH    0x0146
#define PKTPG_LOG_ADDR     0x0150
#define PKTPG_IND_ADDR     0x0158
#define PKTPG_RX_STATUS    0x0400
#define PKTPG_RX_LENGTH    0x0402
#define PKTPG_RX_FRAME     0x0404
#define PKTPG_TX_FRAME     0x0A00


// EEPROM Offsets
#define EEPROM_IND_ADDR_L  0x000D
#define EEPROM_IND_ADDR_M  0x000E
#define EEPROM_IND_ADDR_H  0x000F
#define EEPROM_ISA_CFG     0x001F
#define EEPROM_MEM_BASE    0x0020
#define EEPROM_XMIT_CTL    0x0023
#define EEPROM_ADPTR_CFG   0x0024



// Chip Identification
#define EISA_NUM_CRYSTAL    0x630E
#define PROD_ID_MASK        0xE000
#define PROD_ID_CS8900      0x0000
#define PROD_ID_CS8920      0x4000
#define PROD_ID_CS892X      0x6000
#define PROD_REV_MASK       0x1F00


// Register Numbers
#define REG_NUM_MASK       0x003F
#define REG_NUM_RX_EVENT   0x0004
#define REG_NUM_TX_EVENT   0x0008
#define REG_NUM_BUF_EVENT  0x000C
#define REG_NUM_RX_MISS    0x0010
#define REG_NUM_TX_COL     0x0012


// Self Control Register
#define SELF_CTL_RESET     0x0040
#define SELF_CTL_HC1E      0x2000
#define SELF_CTL_HCB1      0x8000


// Self Status Register
#define SELF_ST_INIT_DONE     0x0080
#define SELF_ST_SI_BUSY       0x0100
#define SELF_ST_EEPROM_PRES   0x0200
#define SELF_ST_EEPROM_OK     0x0400
#define SELF_ST_EL_PRES       0x0800
#define SELF_ST_EEPROM_SIZE   0x1000

// EEPROM Command Register
#define EEPROM_CMD_READ    0x0200
#define EEPROM_CMD_ELSEL   0x0400


// Bus Control Register
#define BUS_CTL_USE_SA     0x0200
#define BUS_CTL_MEM_MODE   0x0400
#define BUS_CTL_IOCHRDY    0x1000
#define BUS_CTL_INT_ENBL   0x8000


// Bus Status Register
#define BUS_ST_TX_BID_ERR  0x0080
#define BUS_ST_RDY4TXNOW   0x0100


// Line Control Register
#define LINE_CTL_RX_ON     0x0040
#define LINE_CTL_TX_ON     0x0080
#define LINE_CTL_AUI_ONLY  0x0100
#define LINE_CTL_10BASET   0x0000


// Test Control Register  
#define TEST_CTL_DIS_LT    0x0080
#define TEST_CTL_ENDEC_LP  0x0200
#define TEST_CTL_AUI_LOOP  0x0400
#define TEST_CTL_DIS_BKOFF 0x0800
#define TEST_CTL_FDX       0x4000


// Receiver Configuration Register  
#define RX_CFG_SKIP        0x0040
#define RX_CFG_RX_OK_IE    0x0100
#define RX_CFG_CRC_ERR_IE  0x1000
#define RX_CFG_RUNT_IE     0x2000
#define RX_CFG_X_DATA_IE   0x4000
#define RX_CFG_ALL_IE      0x7100


// Receiver Event Register  

#define RX_EVENT_DRIBBLE   0x0080
#define RX_EVENT_RX_OK     0x0100
#define RX_EVENT_IND_ADDR  0x0400
#define RX_EVENT_BCAST     0x0800
#define RX_EVENT_CRC_ERR   0x1000
#define RX_EVENT_RUNT      0x2000
#define RX_EVENT_X_DATA    0x4000


// Receiver Control Register 
#define RX_CTL_PROM_A      0x0080
#define RX_CTL_RX_OK_A     0x0100
#define RX_CTL_MCAST_A     0x0200
#define RX_CTL_IND_A       0x0400
#define RX_CTL_BCAST_A     0x0800
#define RX_CTL_CRC_ERR_A   0x1000
#define RX_CTL_RUNT_A      0x2000
#define RX_CTL_X_DATA_A    0x4000


// Transmit Configuration Register  

#define TX_CFG_LOSS_CRS_IE 0x0040
#define TX_CFG_SQE_ERR_IE  0x0080
#define TX_CFG_TX_OK_IE    0x0100
#define TX_CFG_OUT_WIN_IE  0x0200
#define TX_CFG_JABBER_IE   0x0400
#define TX_CFG_16_COLL_IE  0x8000
#define TX_CFG_ALL_IE      0x87C0


// Transmit Event Register  

#define TX_EVENT_LOSS_CRS  0x0040
#define TX_EVENT_SQE_ERR   0x0080
#define TX_EVENT_TX_OK     0x0100
#define TX_EVENT_OUT_WIN   0x0200
#define TX_EVENT_JABBER    0x0400
#define TX_EVENT_COLL_MASK 0x7800
#define TX_EVENT_16_COLL   0x8000


// Transmit Command Register  

#define TX_CMD_START_5     0x0000
#define TX_CMD_START_381   0x0040
#define TX_CMD_START_1021  0x0080
#define TX_CMD_START_ALL   0x00C0
#define TX_CMD_FORCE       0x0100
#define TX_CMD_ONE_COLL    0x0200
#define TX_CMD_NO_CRC      0x1000
#define TX_CMD_NO_PAD      0x2000


// Buffer Configuration Register  

#define BUF_CFG_SW_INT     0x0040
#define BUF_CFG_RDY4TX_IE  0x0100
#define BUF_CFG_TX_UNDR_IE 0x0200
#define BUF_CFG_MISOFLO_IE 0x2000
#define BUF_CFG_COLOFLO_IE 0x1000
#define BUF_CFG_ALL_IE     0x3340

// Buffer Event Register  

#define BUF_EVENT_SW_INT   0x0040
#define BUF_EVENT_RDY4TX   0x0100
#define BUF_EVENT_TX_UNDR  0x0200
#define BUF_EVENT_RX_MISS  0x0400


// ISA Configuration from EEPROM  

#define ISA_CFG_IRQ_MASK   0x000F
#define ISA_CFG_USE_SA     0x0080
#define ISA_CFG_IOCHRDY    0x0100
#define ISA_CFG_MEM_MODE   0x8000


// Memory Base from EEPROM  

#define MEM_BASE_MASK      0xFFF0


// Adapter Configuration from EEPROM  
#define ADPTR_CFG_MEDIA    0x0060
#define ADPTR_CFG_10BASET  0x0020
#define ADPTR_CFG_AUI      0x0040
#define ADPTR_CFG_10BASE2  0x0060
#define ADPTR_CFG_DCDC_POL 0x0080

// Transmission Control from EEPROM  
#define XMIT_CTL_FDX       0x8000

// Default IO Address
#define IO_BASE_ADDRESS    0x0300   

// Media Type

#define MEDIA_AUTO_DETECT       0x00
#define MEDIA_BASE_T            0x01
#define MEDIA_BASE_AUI          0x02
#define MEDIA_BASE_2            0x03
#define MEDIA_PENDING           0xFE
#define MEDIA_NONE              0xFF


// Duplex Mode

#define DUPLEX_AUTO_NEGOTIATE   0x00
#define DUPLEX_HALF             0x01
#define DUPLEX_FULL             0x02
#define DUPLEX_PENDING          0xFE
#define DUPLEX_NONE             0xFF


// Filtering

#define FILTER_INDIVIDUAL_ACCEPT   0x01
#define FILTER_BROADCAST_ACCEPT    0x02
#define FILTER_MULTICAST_ACCEPT    0x04
#define FILTER_PROMISCUOUS_ACCEPT  0x08


// Transmit Errors