📄 os_cpu_a.lst
字号:
FF8E.6 +1 608 CC1_CC11IC_IE BIT CC1_CC11IC.6
FF8E.7 +1 609 CC1_CC11IC_IR BIT CC1_CC11IC.7
FF8E.8 +1 610 CC1_CC11IC_GPX BIT CC1_CC11IC.8
FF90 +1 611 CC1_CC12IC DEFR 0xFF90 ;CAPCOM Channel 12 Interrupt Control Register
FF90.6 +1 612 CC1_CC12IC_IE BIT CC1_CC12IC.6
FF90.7 +1 613 CC1_CC12IC_IR BIT CC1_CC12IC.7
FF90.8 +1 614 CC1_CC12IC_GPX BIT CC1_CC12IC.8
FF92 +1 615 CC1_CC13IC DEFR 0xFF92 ;CAPCOM Channel 13 Interrupt Control Register
FF92.6 +1 616 CC1_CC13IC_IE BIT CC1_CC13IC.6
FF92.7 +1 617 CC1_CC13IC_IR BIT CC1_CC13IC.7
FF92.8 +1 618 CC1_CC13IC_GPX BIT CC1_CC13IC.8
FF94 +1 619 CC1_CC14IC DEFR 0xFF94 ;CAPCOM Channel 14 Interrupt Control Register
FF94.6 +1 620 CC1_CC14IC_IE BIT CC1_CC14IC.6
FF94.7 +1 621 CC1_CC14IC_IR BIT CC1_CC14IC.7
FF94.8 +1 622 CC1_CC14IC_GPX BIT CC1_CC14IC.8
FF96 +1 623 CC1_CC15IC DEFR 0xFF96 ;CAPCOM Channel 15 Interrupt Control Register
FF96.6 +1 624 CC1_CC15IC_IE BIT CC1_CC15IC.6
FF96.7 +1 625 CC1_CC15IC_IR BIT CC1_CC15IC.7
FF96.8 +1 626 CC1_CC15IC_GPX BIT CC1_CC15IC.8
FF98 +1 627 ADC_CIC DEFR 0xFF98 ;ADC End of Conversion Interrupt Control Regi
ster
FF98.6 +1 628 ADC_CIC_IE BIT ADC_CIC.6
FF98.7 +1 629 ADC_CIC_IR BIT ADC_CIC.7
FF98.8 +1 630 ADC_CIC_GPX BIT ADC_CIC.8
FF9A +1 631 ADC_EIC DEFR 0xFF9A ;ADC Overrun Error Control Register
FF9A.6 +1 632 ADC_EIC_IE BIT ADC_EIC.6
FF9A.7 +1 633 ADC_EIC_IR BIT ADC_EIC.7
FF9A.8 +1 634 ADC_EIC_GPX BIT ADC_EIC.8
FF9C +1 635 CC1_T0IC DEFR 0xFF9C ;CAPCOM 1 Timer 0 Interrupt Control Register
FF9C.6 +1 636 CC1_T0IC_IE BIT CC1_T0IC.6
FF9C.7 +1 637 CC1_T0IC_IR BIT CC1_T0IC.7
A166 MACRO ASSEMBLER OS_CPU_A 09/04/2006 10:01:24 PAGE 11
FF9C.8 +1 638 CC1_T0IC_GPX BIT CC1_T0IC.8
FF9E +1 639 CC1_T1IC DEFR 0xFF9E ;CC Timer 1 Interrupt Control Register
FF9E.6 +1 640 CC1_T1IC_IE BIT CC1_T1IC.6
FF9E.7 +1 641 CC1_T1IC_IR BIT CC1_T1IC.7
FF9E.8 +1 642 CC1_T1IC_GPX BIT CC1_T1IC.8
+1 643
+1 644 ; LONDONCORE
+1 645
FFAC +1 646 TFR DEFR 0xFFAC ;Trap Flag Register
FFAC.2 +1 647 TFR_ILLOPA BIT TFR.2
FFAC.3 +1 648 TFR_PRTFLT BIT TFR.3
FFAC.4 +1 649 TFR_PACER BIT TFR.4
FFAC.7 +1 650 TFR_UNDOPC BIT TFR.7
FFAC.12 +1 651 TFR_SOFTBRK BIT TFR.12
FFAC.13 +1 652 TFR_STKUF BIT TFR.13
FFAC.14 +1 653 TFR_STKOF BIT TFR.14
FFAC.15 +1 654 TFR_NMI BIT TFR.15
+1 655
+1 656 ; MAC
+1 657
F000 +1 658 QX0 DEFR 0xF000 ;Offset Register
F002 +1 659 QX1 DEFR 0xF002 ;Offset Register
F004 +1 660 QR0 DEFR 0xF004 ;Offset Register
F006 +1 661 QR1 DEFR 0xF006 ;Offset Register
+1 662
+1 663 ; PEC
+1 664
FEC0 +1 665 PECC0 DEFR 0xFEC0 ;PEC Channel 0 Control Register
FEC2 +1 666 PECC1 DEFR 0xFEC2 ;PEC Channel 1 Control Register
FEC4 +1 667 PECC2 DEFR 0xFEC4 ;PEC Channel 2 Control Register
FEC6 +1 668 PECC3 DEFR 0xFEC6 ;PEC Channel 3 Control Register
FEC8 +1 669 PECC4 DEFR 0xFEC8 ;PEC Channel 4 Control Register
FECA +1 670 PECC5 DEFR 0xFECA ;PEC Channel 5 Control Register
FECC +1 671 PECC6 DEFR 0xFECC ;PEC Channel 6 Control Register
FECE +1 672 PECC7 DEFR 0xFECE ;PEC Channel 7 Control Register
FFA8 +1 673 PECISNC DEFR 0xFFA8 ;PEC Interrupt Subnode Control Register
FFA8.0 +1 674 PECISNC_C0IE BIT PECISNC.0
FFA8.1 +1 675 PECISNC_C0IR BIT PECISNC.1
FFA8.2 +1 676 PECISNC_C1IE BIT PECISNC.2
FFA8.3 +1 677 PECISNC_C1IR BIT PECISNC.3
FFA8.4 +1 678 PECISNC_C2IE BIT PECISNC.4
FFA8.5 +1 679 PECISNC_C2IR BIT PECISNC.5
FFA8.6 +1 680 PECISNC_C3IE BIT PECISNC.6
FFA8.7 +1 681 PECISNC_C3IR BIT PECISNC.7
FFA8.8 +1 682 PECISNC_C4IE BIT PECISNC.8
FFA8.9 +1 683 PECISNC_C4IR BIT PECISNC.9
FFA8.10 +1 684 PECISNC_C5IE BIT PECISNC.10
FFA8.11 +1 685 PECISNC_C5IR BIT PECISNC.11
FFA8.12 +1 686 PECISNC_C6IE BIT PECISNC.12
FFA8.13 +1 687 PECISNC_C6IR BIT PECISNC.13
FFA8.14 +1 688 PECISNC_C7IE BIT PECISNC.14
FFA8.15 +1 689 PECISNC_C7IR BIT PECISNC.15
+1 690
+1 691 ; PORT
+1 692
F080 +1 693 POCON0L DEFR 0xF080 ;Port P0L Output Control Register
F082 +1 694 POCON0H DEFR 0xF082 ;Port P0H Output Control Register
F084 +1 695 POCON1L DEFR 0xF084 ;Port P1L Output Control Register
F086 +1 696 POCON1H DEFR 0xF086 ;Port P1H Output Control Register
F08A +1 697 POCON3 DEFR 0xF08A ;Port P3 Output Control Port
F08C +1 698 POCON4 DEFR 0xF08C ;Port P4 Output Control Port
F094 +1 699 POCON9 DEFR 0xF094 ;Port 9 Output Control Register
F0AA +1 700 POCON20 DEFR 0xF0AA ;Dedicated Pin Output Control Register
F100 +1 701 DP0L DEFR 0xF100 ;P0L Direction Control Register
F100.0 +1 702 DP0L_P0 BIT DP0L.0
F100.1 +1 703 DP0L_P1 BIT DP0L.1
A166 MACRO ASSEMBLER OS_CPU_A 09/04/2006 10:01:24 PAGE 12
F100.2 +1 704 DP0L_P2 BIT DP0L.2
F100.3 +1 705 DP0L_P3 BIT DP0L.3
F100.4 +1 706 DP0L_P4 BIT DP0L.4
F100.5 +1 707 DP0L_P5 BIT DP0L.5
F100.6 +1 708 DP0L_P6 BIT DP0L.6
F100.7 +1 709 DP0L_P7 BIT DP0L.7
F102 +1 710 DP0H DEFR 0xF102 ;P0H Direction Control Register
F102.0 +1 711 DP0H_P0 BIT DP0H.0
F102.1 +1 712 DP0H_P1 BIT DP0H.1
F102.2 +1 713 DP0H_P2 BIT DP0H.2
F102.3 +1 714 DP0H_P3 BIT DP0H.3
F102.4 +1 715 DP0H_P4 BIT DP0H.4
F102.5 +1 716 DP0H_P5 BIT DP0H.5
F102.6 +1 717 DP0H_P6 BIT DP0H.6
F102.7 +1 718 DP0H_P7 BIT DP0H.7
F104 +1 719 DP1L DEFR 0xF104 ;P1L Direction Control Register
F104.0 +1 720 DP1L_P0 BIT DP1L.0
F104.1 +1 721 DP1L_P1 BIT DP1L.1
F104.2 +1 722 DP1L_P2 BIT DP1L.2
F104.3 +1 723 DP1L_P3 BIT DP1L.3
F104.4 +1 724 DP1L_P4 BIT DP1L.4
F104.5 +1 725 DP1L_P5 BIT DP1L.5
F104.6 +1 726 DP1L_P6 BIT DP1L.6
F104.7 +1 727 DP1L_P7 BIT DP1L.7
F106 +1 728 DP1H DEFR 0xF106 ;P1H Direction Control Register
F106.0 +1 729 DP1H_P0 BIT DP1H.0
F106.1 +1 730 DP1H_P1 BIT DP1H.1
F106.2 +1 731 DP1H_P2 BIT DP1H.2
F106.3 +1 732 DP1H_P3 BIT DP1H.3
F106.4 +1 733 DP1H_P4 BIT DP1H.4
F106.5 +1 734 DP1H_P5 BIT DP1H.5
F106.6 +1 735 DP1H_P6 BIT DP1H.6
F106.7 +1 736 DP1H_P7 BIT DP1H.7
F120 +1 737 ALTSEL0P1H DEFR 0xF120 ;Alternate I/O Source 0 Port P1H
F120.0 +1 738 ALTSEL0P1H_P0 BIT ALTSEL0P1H.0
F120.1 +1 739 ALTSEL0P1H_P1 BIT ALTSEL0P1H.1
F120.2 +1 740 ALTSEL0P1H_P2 BIT ALTSEL0P1H.2
F120.3 +1 741 ALTSEL0P1H_P3 BIT ALTSEL0P1H.3
F120.4 +1 742 ALTSEL0P1H_P4 BIT ALTSEL0P1H.4
F120.5 +1 743 ALTSEL0P1H_P5 BIT ALTSEL0P1H.5
F120.6 +1 744 ALTSEL0P1H_P6 BIT ALTSEL0P1H.6
F120.7 +1 745 ALTSEL0P1H_P7 BIT ALTSEL0P1H.7
F126 +1 746 ALTSEL0P3 DEFR 0xF126 ;Alternate I/O Source Port 3 Selection
F126.1 +1 747 ALTSEL0P3_P1 BIT ALTSEL0P3.1
F126.3 +1 748 ALTSEL0P3_P3 BIT ALTSEL0P3.3
F126.8 +1 749 ALTSEL0P3_P8 BIT ALTSEL0P3.8
F126.9 +1 750 ALTSEL0P3_P9 BIT ALTSEL0P3.9
F126.10 +1 751 ALTSEL0P3_P10 BIT ALTSEL0P3.10
F126.11 +1 752 ALTSEL0P3_P11 BIT ALTSEL0P3.11
F126.13 +1 753 ALTSEL0P3_P13 BIT ALTSEL0P3.13
F128 +1 754 ALTSEL1P3 DEFR 0xF128 ;Alternate I/O Source 1 Port P3
F128.1 +1 755 ALTSEL1P3_P1 BIT ALTSEL1P3.1
F12A +1 756 ALTSEL0P4 DEFR 0xF12A ;Alternate I/O Source 0 Port P4
F12A.6 +1 757 ALTSEL0P4_P6 BIT ALTSEL0P4.6
F12A.7 +1 758 ALTSEL0P4_P7 BIT ALTSEL0P4.7
F130 +1 759 ALTSEL0P1L DEFR 0xF130 ;P1L Alternate Select Register 0
F130.0 +1 760 ALTSE⌨️ 快捷键说明
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