📄 start_v2.lst
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642 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
643 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 644 _BTYP1 EQU 2 ; 0 = 8 bit Demultiplexed bus
645 ; 1 = 8 bit Multiplexed bus
646 ; 2 = 16 bit Demultiplexed bus
647 ; 3 = 16 bit Multiplexed bus
648 ;</h>
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 11
649 ;
650 ; <h>TCONCS1: Definitions for the Timing Configuration register
651 ; ==========================================================
652 ;
653 ; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
0000 654 _PHA1 EQU 0 ; 0 = 0 clock cycles
655 ; : = :
656 ; 3 = 3 clock cycles
657 ;
658 ; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
0000 659 _PHB1 EQU 0 ; 0 = 1 clock cycle
660 ; 1 = 2 clock cycles
661 ;
662 ; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
0000 663 _PHC1 EQU 0 ; 0 = 0 clock cycles
664 ; : = :
665 ; 3 = 3 clock cycles
666 ;
667 ; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
0000 668 _PHD1 EQU 0 ; 0 = 0 clock cycles
669 ; 1 = 1 clock cycle
670 ;
671 ; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
0008 672 _PHE1 EQU 8 ; 0 = 1 clock cycle
673 ; : = :
674 ; 31 = 32 clock cycles
675 ;
676 ; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
0000 677 _RDPHF1 EQU 0 ; 0 = 0 clock cycles
678 ; : = :
679 ; 3 = 3 clock cycles
680 ;
681 ; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
0003 682 _WRPHF1 EQU 3 ; 0 = 0 clock cycles
683 ; : = :
684 ; 3 = 3 clock cycles
685 ;</h> </e>
686 ;
687 ;<e>Configure External Bus Behaviour for CS2 Area
688 ; =============================================
689 ;
690 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
691 $SET (CONFIG_CS2 = 0)
692 ;
693 ; <h>Definitions for Address Select register ADDRSEL2
694 ; ===================================================
695 ; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
00200000 696 _ADDR2 EQU 0x200000 ; Set CS2# Start Address (default 100000H)
697
698 ; <o> CS2 Size in KB
699 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
700 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
701 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 702 _SIZE2 EQU 1024*KB ; Set CS2# Size (default 1024*KB = 1*MB)
703 ; possible values for _SIZE2 are:
704 ; 4*KB (gives RGSZ2 = 0)
705 ; 8*KB (gives RGSZ2 = 1)
706 ; 16*KB (gives RGSZ2 = 2)
707 ; 32*KB (gives RGSZ2 = 3)
708 ; 64*KB (gives RGSZ2 = 4)
709 ; 128*KB (gives RGSZ2 = 5)
710 ; 256*KB (gives RGSZ2 = 6)
711 ; 512*KB (gives RGSZ2 = 7)
712 ; 1024*KB or 1*MB (gives RGSZ2 = 8)
713 ; 2048*KB or 2*MB (gives RGSZ2 = 9)
714 ; 4096*KB or 4*MB (gives RGSZ2 = 10)
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 12
715 ; 8192*KB or 8*MB (gives RGSZ2 = 11)
716 ; (RGSZ2 = 12 .. 15 reserved)
717 ;</h>
718 ;
719 ; <h>Definitions for Function Configuration Register FCONCS2
720 ; =======================================================
721 ;
722 ; <q> ENCS2: Enable Chip Select (FCONCS2.0)
0001 723 _ENCS2 EQU 1 ; 0 = Chip Select 0 disabled
724 ; 1 = Chip Select 0 enabled
725 ;
726 ; <q> RDYEN2: Ready Enable (FCONCS2.1)
0000 727 _RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1
728 ; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
729 ;
730 ; <o> RDYMOD2: Ready Mode (FCONCS2.2)
731 ; <0=> Asynchronous <1=> Synchronous
0000 732 _RDYMOD2 EQU 0 ; 0 = Asynchronous READY
733 ; 1 = Synchronous READY
734 ;
735 ; <o> BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
736 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
737 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 738 _BTYP2 EQU 2 ; 0 = 8 bit Demultiplexed bus
739 ; 1 = 8 bit Multiplexed bus
740 ; 2 = 16 bit Demultiplexed bus
741 ; 3 = 16 bit Multiplexed bus
742 ;</h>
743 ;
744 ; <h>TCONCS2: Definitions for the Timing Configuration register
745 ; ==========================================================
746 ;
747 ; <o>PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1) <0-3>
0000 748 _PHA2 EQU 0 ; 0 = 0 clock cycles
749 ; : = :
750 ; 3 = 3 clock cycles
751 ;
752 ; <o>PHB2: Phase B clock cycle (TCONCS2.2) <1-2> <#-1>
0000 753 _PHB2 EQU 0 ; 0 = 1 clock cycle
754 ; 1 = 2 clock cycles
755 ;
756 ; <o>PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4) <0-3>
0000 757 _PHC2 EQU 0 ; 0 = 0 clock cycles
758 ; : = :
759 ; 3 = 3 clock cycles
760 ;
761 ; <o>PHD2: Phase D clock cycle (TCONCS2.5) <0-1>
0000 762 _PHD2 EQU 0 ; 0 = 0 clock cycles
763 ; 1 = 1 clock cycle
764 ;
765 ; <o> PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10) <1-32> <#-1>
0008 766 _PHE2 EQU 8 ; 0 = 1 clock cycle
767 ; : = :
768 ; 31 = 32 clock cycles
769 ;
770 ; <o>RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12) <0-3>
0000 771 _RDPHF2 EQU 0 ; 0 = 0 clock cycles
772 ; : = :
773 ; 3 = 3 clock cycles
774 ;
775 ; <o>WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14) <0-3>
0003 776 _WRPHF2 EQU 3 ; 0 = 0 clock cycles
777 ; : = :
778 ; 3 = 3 clock cycles
779 ;</h> </e>
780 ;
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 13
781 ;<e>Configure External Bus Behaviour for CS3 Area
782 ; =============================================
783 ;
784 ; --- Set CONFIG_CS3 = 1 to initialize the ADDRSEL3/FCONCS3/TCONCS3 registers
785 $SET (CONFIG_CS3 = 0)
786 ;
787 ; <h>Definitions for Address Select register ADDRSEL3
788 ; ===================================================
789 ; <o> CS3 Start Address <0x0-0xFFFFFF:0x1000>
00300000 790 _ADDR3 EQU 0x300000 ; Set CS3# Start Address (default 100000H)
791
792 ; <o> CS2 Size in KB
793 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
794 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
795 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 796 _SIZE3 EQU 1024*KB ; Set CS3# Size (default 1024*KB = 1*MB)
797 ; possible values for _SIZE3 are:
798 ; 4*KB (gives RGSZ3 = 0)
799 ; 8*KB (gives RGSZ3 = 1)
800 ; 16*KB (gives RGSZ3 = 2)
801 ; 32*KB (gives RGSZ3 = 3)
802 ; 64*KB ⌨️ 快捷键说明
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