📄 start_v2.lst
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0000 320 _RORMV EQU 0 ; 0 = RSTOUT delivers RSTOUT# signal
321 ; 1 = RSTOUT pin operates as GPIO
322 ;
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 6
323 ; <o> ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
324 ; <0=>RSTOUT deactivated by user software <1=>RSTOUT deactivated after reset
0000 325 _ROCOFF EQU 0 ; 0 = RSTOUT is deactivated by user software
326 ; 1 = RSTOUT is deactivated at end of reset
327 ;
328 ; <o> ROCON: RSTOUT# Control Switch Off (RSTCON.6)
329 ; <0=> RSTOUT active on any reset <1=> RSTOUT active on hardware reset
0000 330 _ROCON EQU 0 ; 0 = RSTOUT is activated upon any reset
331 ; 1 = RSTOUT is only activated upon a hardware reset
332 ;
333 ; <q> RODIS: RSTOUT# Disable Control (RSTCON.7) <0-1>
0000 334 _RODIS EQU 0 ; 0 = RSTOUT is controlled by other mechanism
335 ; 1 = RSTOUT is deactivated
336 ;
337 ;</e>
338 ;
339 ;
340 ; <e> Definitions for PLL Control Register PLLCON
341 ; ===============================================
342 ;
343 ; INIT_PLLCON: Init PLLCON register
344 ; --- Set INIT_PLLCON = 0 to initilize the PLLCON register
345 $SET (INIT_PLLCON = 0)
346 ;
347 ; <o> PLLODIV: PLL Output Divider (PLLCON.0 .. PLLCON.3) <0-14>
0004 348 _PLLODIV EQU 4 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1)
349 ; 15 = reserved
350 ;
351 ; <o> PLLIDIV: PLL Input Divider (PLLCON.4 .. PLLCON.5) <0-3>
352 ; <i> Fin = Fosc / (PLLIDIV+1)
0000 353 _PLLIDIV EQU 0 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1)
354 ;
355 ; <o> PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
356 ; <0=> Ouput:100-150MHz / Base:20-80MHz <1=> Ouput:150-200MHz / Base:40-130MHz
357 ; <2=> Ouput:200-250MHz / Base:60-180MHz <3=> (250...300 MHz) Reserved
0002 358 _PLLVB EQU 2 ; ValueVCO output frequency Base frequency
359 ; 0 = 100...150 MHz 20...80 MHz
360 ; 1 = 150...200 MHz 40...130 MHz
361 ; 2 = 200...250 MHz [def.] 60...180 MHz
362 ; 3 = (250...300 MHz) Reserved
363 ;
364 ; <o> PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12) <6-31>
365 ; <i> Fvco = Fin * (PLLMUL+1)
0018 366 _PLLMUL EQU 24 ; 7 .. 31 Fvco = Fin * (PLLMUL+1)
367 ; 0 .. 6 = reserved
368 ;
369 ; <o> PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
370 ; <0=> Bypass PLL clock mult., the VCO is off <1=> Bypass PLL clock mult., the VCO i
s running
371 ; <2=> VCO clock used, input clock switched off <3=> VCO clock used, input clock conne
cted
0003 372 _PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off
373 ; 1 = Bypass PLL clock mult., the VCO is running
374 ; 2 = VCO clock used, input clock switched off
375 ; 3 = VCO clock used, input clock connected
376 ;
377 ; <o> PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
378 ; <0=> Register PLLCON may be written <1=> Write cycles to register PLLCON are ignore
d
0000 379 _PLLWRI EQU 0 ; 0 = Register PLLCON may be written
380 ; 1 = Write cycles to register PLLCON are ignored
381 ;</e>
382 ;
383 ; <e> Definitions for Watchdog Timer Control Register WDTCON
384 ; ==========================================================
385 ;
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 7
386 ; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initilize the WDTCON regist
er
387 $SET (WATCHDOG = 0) ; 0 = Disabled Hardware watchdog
388 ;
389 ; <o> WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
390 ; <0=> Peripheral Frequency divided by 2 <1=> Peripheral Frequency divided by 128
391 ; <2=> Peripheral Frequency divided by 4 <3=> Peripheral Frequency divided by 256
0001 392 _WDTIN EQU 1 ; 0 = frequency f_peripheral / 2 (CPU default)
393 ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
394 ; 2 = frequency f_peripheral / 4
395 ; 3 = frequency f_peripheral / 256
396 ;
397 ; <o> WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15) <0-255>
398 ; <i> High byte of WDT (counts up, overflow gives Watchdog reset)
0000 399 _WDTREL EQU 0
400 ;
401 ;</e>
402 ; <e> Definitions for Frequency Output Signal FOCON
403 ; =================================================
404 ;
405 ; INIT_FOCON: Init FOCON register
406 ; --- Set INIT_FOCON = 0 to initilize the FOCON register
407 $SET (INIT_FOCON = 1)
408 ;
409 ; <o> CLKEN: CLKOUT Enable (FOCON.7)
410 ; <0=> P3.15 is IO <1=> P3.15 is CLKOUT
0000 411 _CLKEN EQU 0 ; 0 = P3.15 is IO pin when _FOUT is 0
412 ; 1 = P3.15 outputs signal CLKOUT
413 ;
414 ; <o> FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13) <0-63>
415 ; <i> Is copied to FOCNT upon each underflow of FOCNT
0000 416 _FORV EQU 0
417 ;
418 ; <o> FOSS: Frequency Output Signal Select (FOCON.14)
419 ; <0=> Output of Toggle Latch <1=> Output of Reload Counter
0000 420 _FOSS EQU 0 ; 0 = Output of the toggle latch; 0.5 duty cycle
421 ; 1 = Output of reload counter; duty cycle depends on FORV
422 ;
423 ; <o> FOEN: Frequency Output Enable (FOCON.15)
424 ; <0=> P3.15 is IO <1=> P3.15 outputs f_OUT
0000 425 _FOEN EQU 0 ; 0 = P3.15 is IO pin when _CLKEN is 0
426 ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
427 ;</e>
428 ;
429 ;<h> External Bus Configuration
430 ;
431 ; <e> Configure External Bus (EBC) Behaviour
432 ; ==========================================
433 ;
434 ; --- Set CONFIG_EBC = 0 to initialize the EBCMOD0/EBCMOD1 registers
435 $SET (CONFIG_EBC = 0) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the
436 ; of configuration bus (typical Port0) values.
437 ; 1 = the following external bus configuration values
438 ; are written to EBCMOD and BUSACT0
439 ;
440 ; <h> Definitions for EBC Mode 0 register EBCMOD0
441 ; ===============================================
442 ;
443 ; <o> SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3) <0-8>
444 ; <i> Number of active Address Lines (A16-A23)
0000 445 _SAPEN EQU 0 ; 0 = No segment address pins enabled
446 ; 1 = One (A16) segment address pin enabled
447 ; : = :
448 ; 8 = Eight (A16 .. A23) address pins enabled
449 ; 9 - 15 = reserved
450 ;
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 8
451 ; <o> CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7) <0-8>
452 ; <i> Number of active ChipSelect pins
0008 453 _CSPEN EQU 8 ; 0 = No CS pins enabled
454 ; 1 = One CS (CS0) pin enabled
455 ; : = :
456 ; 8 = Eight CS (CS0 .. CS7) pins enabled
457 ; 9 - 15 = reserved
458 ; Note: the number of available CS pins depends on the chip used
459 ;
460 ; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
0000 461 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
462 ; 1 = HOLD, HLDA and BREQ pins act normally
463 ;
464 ; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
465 ; <0=> Master Mode <1=> Slave Mode
0000 466 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode
467 ; 1 = Bus arbiter acts in slave mode
468 ;
469 ; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
0000 470 _EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus
471 ; 1 = EBC off (pins to be used as GPIO if implemented)
472 ;
473 ; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
474 ; <0=> WR and BHE <1=> WRL and WRH
0000 475 _WRCFG EQU 0 ; 0 = Pins act as WR and BHE
476 ; 1 = Pins act as WRL and WRH
477 ;
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