📄 start_v2.lst
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0001 156 _OVRUN EQU 1 ; 0 = Overrun of Pipeline Bubbles not allowed
157 ; 1 = Overrun of Pipeline Bubbles allowed
158 ;
159 ; <q> ZSC: Enable Zero Cycle Jump Cache (CPUCON2.5)
0001 160 _ZSC EQU 1 ; 0 = Zero Cycle Jump Cache disabled
161 ; 1 = Zero Cycle Jump Cache enabled
162 ;
163 ; <q> STEN: Enable Stall Instruction (CPUCON2.6)
0000 164 _STEN EQU 0 ; 0 = Stall instruction disabled
165 ; 1 = Stall instruction enabled
166 ;
167 ; <q> EIOIAEN: Early IO Injection Acknowledge guaranteed (CPUCON2.7)
0001 168 _EIOIAEN EQU 1 ; 0 = Injection ack. by destructive read not guaranteed
169 ; ; 1 = Injection ack. by destructive read guaranteed
170 ;
171 ; <q> BYPF: Enable Fetch Bypass Control (CPUCON2.8)
0001 172 _BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled
173 ; 1 = Bypass Path from Fetch to Decode enabled
174 ;
175 ; <q> BYPPF: Enable Prefecth Bypass Control (CPUCON2.9)
0001 176 _BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled
177 ; 1 = Bypass Path from Prefetch to Decode enabled
178 ;
179 ; <o> FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
180 ; <0=> FIFO disabled <1=> 1 instruction
181 ; <2=> 2 instructions <3=> 3 instructions
0003 182 _FIFOFED EQU 3 ; 0 = FIFO disabled
183 ; 1 = FIFO filled with up to 1 instruction per cycle
184 ; 2 = FIFO filled with up to 2 instructions per cycle
185 ; 3 = FIFO filled with up to 3 instructions per cycle
186 ;
187 ;<o> FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15) <0-8>
0008 188 _FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO)
189 ; 1 = 1 FIFO entry
190 ; ...
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 4
191 ; 8 = 8 FIFO entries
192 ; 9 - 15 = reserved
193 ;</e>
194
195 ; <e> Definitions for Internal Memory Block Control Register IMBCTR
196 ; =================================================================
197 ;
198 ; INIT_IMBCTR: Init IMBCTR register
199 ; --- <i>Set INIT_IMBCTR to initilize the IMBCTR register
200 $SET (INIT_IMBCTR = 0) ; default: do not initilize IMBCTR
201 ;
202 ; <o> WSFLASH: Wait States for the Flash Memory (IMBCTR.0 .. IMBCTR.1)
203 ; <0=> No waitstates (Flash Read in one clock)
204 ; <1=> One waitstate (Flash Read in two clocks)
205 ; <2=> Two waitstates (Flash Read in three clocks)
206 ; <3=> Three waitstates (Flash Read in four clocks)
0001 207 _WSFLASH EQU 1 ; 0 = No waitstates
208 ; 1 = One waitstate
209 ; 2 = Two waitstates
210 ; 3 = Three waitstates
211 ;
212 ; <q> WSRAM: Wait State for Program RAM Access (IMBCTR.2)
213 ; <i> when enabled, Program SRAM has same timing behaviour as Flash memory
0000 214 _WSRAM EQU 0 ; 0 = Program SRAM accessed with max. speed
215 ; 1 = Program SRAM access like Flash Memory
216 ;
217 ;</e>
218
219 ;</h>
220 ; <h> Peripheral Configuration
221 ; ============================
222 ;
223 ; <e> Definitions for System Configuration Register SYSCON1
224 ; =========================================================
225 ;
226 ; INIT_SYSCON1: Init SYSCON1 register
227 ; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON1 register
228 $SET (INIT_SYSCON1 = 0)
229 ;
230 ; <q> SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
231 ; <0=> IDLE mode upon IDLE instr. <1=> SLEEP mode upon IDLE instr.
0000 232 _SLEEPCON EQU 0 ; 0 = Normal IDLE mode entered upone IDLE instruction
233 ; 1 = SLEEP mode entered upon IDLE instruction
234 ; 2 - 3 = reserved
235 ;
236 ; <q> PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
237 ; <0=>Port drivers are always ON <1=>Port drivers are off in IDLE/Sleep mode
238 ; <2=>Port drivers are off in Powerdown mode
0000 239 _PDCFG EQU 0 ; 0 = Port drivers are always ON (default)
240 ; 1 = Port drivers are off in IDLE or Sleep mode
241 ; 2 = Port drivers are off in Powerdown mode
242 ; 3 = reserved
243 ;
244 ; <o> PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
245 ; <0=> Program Flash always ON <1=>Program Flash OFF in IDLE/Sleep mode
0000 246 _PFCFG EQU 0 ; 0 = Program Flash is always ON (default)
247 ; 1 = Program Flash is off in IDLE or Sleep mode
248 ; 2 - 3 = reserved
249 ;
250 ; <o> CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
251 ; <0=>CPU clock = PLL frequency <1=>CPU clock = PLL frequency / 2
0000 252 _CPSYS EQU 0 ; 0 = clock signal for CPU is PLL frequency
253 ; 1 = clock signal for CPU is PLL frequency / 2
254 ; 2 - 7 = reserved
255 ; </e>
256 ;
A166 MACRO ASSEMBLER START_V2 08/31/2006 11:40:34 PAGE 5
257 ; <e> Definitions for System Configuration Register SYSCON3
258 ; =========================================================
259 ;
260 ; INIT_SYSCON3: Init SYSCON3 register
261 ; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
262 $SET (INIT_SYSCON3 = 1)
263 ;
264 ; SYSCON3: Power Management (disable on-chip peripherals)
265 ;
266 ;<q> Disable Analog/Digital Converter
0000 267 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0)
268 ;<q> Disable UART ASC0
0000 269 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1)
270 ;<q> Disable Synchronus Serial Cnl0 SSC0
0000 271 SSC0DIS EQU 0 ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2)
272 ;<q> Disable Timer Block GPT
0000 273 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3)
274 ; reserved (SYSCON3.4)
275 ;<q> Disable on-chip Flash Memory Module
0000 276 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
277 ;<q> Disable CAPCOM Unit 1
0000 278 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6)
279 ;<q> Disable CAPCOM Unit 2
0000 280 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7)
281 ;<q> Disable CAPCOM Unit 6
0000 282 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8)
283 ; reserved (SYSCON3.9)
284 ;<q> Disable UART ASC1
0000 285 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10)
286 ;<q> Disable I2C Bus Module
0000 287 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11)
288 ;<q> Disable SDLM (J1850) Module
0000 289 SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12)
290 ;<q> Disable on-chip CAN Module
0000 291 CANDIS EQU 0 ; 1 = disable on-chip CAN Module (SYSCON3.13)
292 ;<q> Disable Real Time Clock
0000 293 RTCDIS EQU 0 ; 1 = disable Real Time Clock (SYSCON3.14)
294 ;<q> Disable Synchronus Serial Cnl1 SSC1
0000 295 SSC1DIS EQU 0 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
296 ;
297 ;</e>
298 ;</h>
299 ; <e> Definitions for Reset Configuration Register RSTCON
300 ; =======================================================
301 ;
302 ; INIT_RSTCON: Init RSTCON register
303 ; --- Set INIT_RSTCON = 0 to initilize the RSTCON register
304 $SET (INIT_RSTCON = 1)
305 ;
306 ; <o> RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
307 ; <0=> 2 CPU clocks <1=> 4 CPU clocks <2=> 8 CPU clocks <3=> 16 CPU clocks
308 ; <4=> 32 CPU clocks <5=> 64 CPU clocks <6=> 128 CPU clocks <7=> 256 CPU clocks
0000 309 _RSTLEN EQU 0 ; 0 = 2 t_CPU clocks (default)
310 ; 1 = 4 t_CPU clocks
311 ; 2 = 8 t_CPU clocks
312 ; 3 = 16 t_CPU clocks
313 ; 4 = 32 t_CPU clocks
314 ; 5 = 64 t_CPU clocks
315 ; 6 = 128 t_CPU clocks
316 ; 7 = 256 t_CPU clocks
317 ;
318 ; <o> RORMV: RSTOUT# Remove Control (RSTCON.4)
319 ; <0=> RSTOUT delivers RSTOUT# signal <1=> RSTOUT pin operates as GPIO
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