📄 key_arm_rd.v
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module key_arm_rd(clk,clr,key_value,key_flag,
addr,ncs,nwe,data,rd_enable);
input clk;
input clr;
input[7:0] key_value;
input key_flag;
input[5:0] addr;
input ncs;
input nwe;
output[7:0] data;
output rd_enable;
reg[7:0] data;
reg rd_enable;
reg rd_en,rd_en1,rd_en2;
//ARM read key board value
always @ (posedge clk or posedge clr)
if(clr)
data = 8'bz;
else if((addr == 6'b000010) && !ncs && !nwe)
data = key_value;
else if((addr == 6'b000100) && !ncs && !nwe)
data = {7'b0,key_flag};
else
data = 8'bz;
always @ (posedge clk or posedge clr)
if(clr)
rd_en = 1'b0;
else if((addr == 6'b000010) && !ncs && !nwe)
rd_en = 1'b1;
else
rd_en = 1'b0;
always @ (posedge clk or posedge clr)
if(clr)
begin
rd_en1 <= 1'b1;
rd_en2 <= 1'b1;
end
else
begin
rd_en1 <= rd_en;
rd_en2 <= rd_en1;
end
always @ (posedge clk or posedge clr)
if(clr)
rd_enable = 1'b0;
else if(!rd_en2 && rd_en1)
rd_enable = 1'b1;
else
rd_enable = 1'b0;
endmodule
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