key_comp.v

本文件用于spi接口的键盘扫描模块

module key_comp(clk,
				clr,
				din,
				reset,
				clk500k,
				key_data,
				key_enable);
	input       clk;
	input       clr;
	input       din;
	output      reset;
	output      clk500k;
	output[7:0] key_data;
	output      key_enable;
		
	reg[7:0]    count256;
	reg[6:0]    count128;
	wire        reset;
	wire        clk500k;
	reg         reset1,reset2;
	reg[63:0]   key_reg0;
	reg[63:0]   key_reg1;
	reg[63:0]   key_reg2;
	reg[5:0]	key_count0;
	reg[5:0]	key_count1;
	reg[5:0]	key_count2;
	reg[63:0]   key_comp_en;
	reg[7:0]    key_data;
	reg         clk500_1,clk500_2;
	reg         key_change;
	reg         key_enable;
	reg         key_enable1,key_enable2;
	
	//Generate 500k clock
	always @ (posedge clk or posedge clr)
		if(clr)
			count256 = 8'b0;
		else
			count256 = count256 + 1;
			
	assign clk500k = count256[7];
			
	always @ (posedge clk or posedge clr)
		if(clr)
			begin
				clk500_1 <= 1'b1;
				clk500_2 <= 1'b1;
			end
		else
			begin
				clk500_1 <= clk500k;
				clk500_2 <= clk500_1;
			end
		
	//clk500k 128 divide frequency, and generate reset signal
	always @ (posedge clk or posedge clr)
		if(clr)
			count128 = 7'b0;
		else if(!clk500_2 && clk500_1)
			count128 = count128 + 7'b1;
			
	assign reset = count128[6];
	
	always @ (posedge clk or posedge clr)
		if(clr)
			begin
				reset1 <= 1'b1;
				reset2 <= 1'b1;
			end
		else
			begin
				reset1 <= reset;
				reset2 <= reset1;
			end
	
	//Register 0
	always @ (posedge clk or posedge clr)
		if(clr)
			begin
				key_count0 = 6'b0;
				key_reg0   = 64'b0;
			end
		else if(!reset)
			begin
				if(!clk500_2 && clk500_1)
					begin
						key_reg0[key_count0] = din;
						key_count0           = key_count0 + 1;
					end 
			end
		else
				key_count0 = 6'b0;
		
	//Register 1	
	always @ (posedge clk or posedge clr)
		if(clr)
			begin
				key_count1  = 6'b0;
				key_reg1    = 64'b0;  
				key_comp_en = 64'b0;
			end
		else if(!reset1)
			begin
				if(!clk500_2 && clk500_1)
					begin 
						key_comp_en[key_count1] = 
							(key_reg0[key_count1] == key_reg1[key_count1]) ? 1'b1:1'b0;
						key_reg1[key_count1]    = key_reg0[key_count1];//key_count0
						key_count1              = key_count1 + 6'b000001;
					end
			end
		else
			key_count1 = 6'b0;
		
	//Register 2
	always @ (posedge clk or posedge clr)
		if(clr)
			begin
				key_count2 = 6'b0;
				key_reg2   = 64'b0;
			end
		else if(!reset2)
			begin
				if(!clk500_2 && clk500_1)
					begin
						if(key_comp_en[key_count2])
							begin
								if((key_reg2[key_count2] != key_reg1[key_count2]))
									begin
										key_reg2[key_count2] = key_reg1[key_count2];
										key_change 			 = 1'b1;
										key_data = {1'b0,(key_count2 + + 5'b00001),key_reg1[key_count2]};
									end//
								else
								key_change = 1'b0;
							end
						key_count2 = key_count2 + 1; 
					end
				else
				key_change = 1'b0;	
			end
		else
			begin
				key_count2 = 6'b0;
				key_change = 1'b0;
			end	
	
	//fifo write enalble			
	//always @ (posedge clk or posedge clr)
	//	if(clr)
	//		begin
	//			key_enable1 <= 1'b1;
	//			key_enable2 <= 1'b1;
	//		end
	//	else
	//		begin
	//			key_enable1 <= key_change;
	//			key_enable2 <= key_enable1;
	//		end
			
	always @ (posedge clk or posedge clr)
		if(clr)
			key_enable = 1'b0;
		else //if(!key_enable2 && key_enable1)
			key_enable = key_change;//1'b1;
		//else
		//	key_enable = 1'b0;
			
endmodule