dmathery.doc

MMURTL(tm) Computer Operating System Ver x0.8, source code.

Copyright (c) 1991-1993, R.A. Burgess

DMA Theory of operation

1. Introduction

This provides a description of how MMURTL handles the DMA hardware on the ISA/EISA machines.

The following abbreviations are used in port names in the small section of code that defines them below:
   St	= Status
   Cmd	= Command
   Msk	= Mask
   Rq	= Request
   Add 	= Address
   Cnt 	= Count  (Used for Word Count)
   Rd	= Read
   W		= Write
   Bt	= Bits

Port addresses and page registers

DMA 1 Port Addresses

DMA10Add		EQU  00h	;Ch 0 Address
DMA10Cnt		EQU  01h	;Ch 0 Word Count
DMA11Add		EQU  02h	;Ch 1 Address
DMA11Cnt		EQU  03h	;Ch 1 Word Count
DMA12Add		EQU  04h	;Ch 2 Address
DMA12Cnt		EQU  05h	;Ch 2 Word Count
DMA13Add		EQU  06h	;Ch 3 Address
DMA13Cnt		EQU  07h	;Ch 3 Word Count
DMA1StatCmd	EQU  08h	;Read Status/Write Command
DMA1RqReg		EQU  09h	;Read/Write DMA Rq Register
DMA1RCmdWbm	EQU  0Ah	;Read Command/Write Single bit mask
DMA1Mode		EQU  0Bh	;Read/Write Mode register
DMA1FF		EQU  0Ch	;Writing this address clears 
					byte ptr flip flop
DMA1Clear		EQU  0Dh	;Write causes MASTER Clear 
					(Read from Temp Reg)
DMA1ClrMode	EQU  0Eh	;Rd clears mode reg count/Wr 
					Clr ALL mask bits
DMA1MskBts	EQU  0Fh	;Read/Write DMA Rq Mask Register

DMA 2 Port addresses

DMA20Add		EQU  0C0h ;Ch 0 Address
DMA20Cnt		EQU  0C2h ;Ch 0 Word Count
DMA21Add		EQU  0C4h ;Ch 1 Address
DMA21Cnt		EQU  0C6h ;Ch 1 Word Count
DMA22Add		EQU  0C8h ;Ch 2 Address
DMA22Cnt		EQU  0CAh ;Ch 2 Word Count
DMA23Add		EQU  0CCh ;Ch 3 Address
DMA23Cnt		EQU  0CEh ;Ch 3 Word Count
DMA2StatCmd	EQU  0D0h ;Read Status/Write Command
DMA2RqReg		EQU  0D2h ;Read/Write DMA Rq Register
DMA2RdCmdWb	EQU  0D4h ;Read Command/Write Single bit mask
DMA2Mode		EQU  0D6h ;Read/Write Mode register
DMA2FF		EQU  0D8h ;Writing this address clears 
					byte ptr flip flop
DMA2Clear		EQU  0DAh ;Write causes MASTER Clear 
					(Read from Temp Reg)
DMA2ClrMode	EQU  0DCh ;Rd clears mode reg count/Wr 
					Clr ALL mask bits
DMA2MskBts	EQU  0DEh ;Read/Write DMA Rq Mask Register

DMA Page register by DRQ/DACK number

DMAPage0	EQU 87h		;DMA DACK0 Page register
DMAPage1	EQU 83h
DMAPage2	EQU 81h
DMAPage3	EQU 82h
DMAPage5	EQU 8Bh
DMAPage6	EQU 89h
DMAPage7	EQU 8Ah


We don't set the Command Register of the DMA controller because this has been pre-programmed by the ROM for proper operation. In other words we don't do a master clear!  

Actually the command register bits are all 0 (cleared) for normal operation anyway.  The only ones we are concerend with are the DMA disable (bit 2) which we don't use cause it shuts down all channels of the DMA and there is no need to do this to program just one channel (even though the harware documentation say you can do it this way).

The steps we follow to program a channel in a multitasking environment follows:

1) Set the Mask bit for the channel to program (prevents DRQ in)

2) Set Mode for the channel you are programming (read or write)

3) CLI (stop INTs as it may cause DMA programming on another channel and would interfere with byte ptr flip flop...)

4) Write to port xx to clear byte pointer flip flop (value out meaningless)

5) Write lobyte base address (0-7)

6) Write hibyte base address (8-15)

7) Write bits 16-23 to page register for current channel

8) Write lobyte count  (0-7 - remember, count is one less than number to move)

9) Write hibyte of count (8-15)

10) STI

11) Clear the Mask Bit for the affected DMA channel so it will operate

12) Program the device (floppy disk or comms) to move the data


DMA Channel Usage

The Floppy is on channel 2 of the first DMA comtroller (Slave DMA).  This is the only internal usage of DMA.

------------------ End of DMA Theory --------------------